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Introducing the Facility Asynchronous Data Analysis Tool (FADAT) to optimize productive machine cycle in industrial plants

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IFAC-PapersOnLine 2016年第30期49卷 302-307页

作者： Fritscher, Michael Aschenbrenner, Doris Sittner, Felix Krauß, Markus Schilling, Klaus The authors are with the Zentrum für Telematik e.V. Würzburg97074 Germany Klaus Schilling is head of Chair VII at the Department of Computer Science University of Würzburg Würzburg97074 Germany

The main focus of this paper is a generic approach to enable both single persons and worldwide distributed teams to analyse and enhance manufacturing plants. This paper describes the state of the art, current challenges, our approach to tackle this task, a first implementation of our solution (FADAT) and the test results from at a real industrial plant. The novelties are the combination and synchronisation of different data sources for analysing plans and the implementation of a collaborative working mode without the need for a steady online connection. © 2016

关键词： Industrial plants computer debugging Data handling Distributed computer systems Industrial robots Information analysis Program debugging Asynchronous data Collaborative working Data handling systems Data stream Distributed teams Human Machine Interface Manufacturing plant State of the art

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Simulation and Satisfiability Guided Counter-example Triage for RTL Design debugging

Simulation and Satisfiability Guided Counter-example Triage ...

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15th International Symposium on Quality Electronic Design (ISQED)

作者： Poulos, Zissis Yang, Yu-Shen Veneris, Andreas Le, Bao Univ Toronto Dept ECE Toronto ON Canada Adv Micro Devices Inc Toronto ON Canada

ISBN: (纸本)9781479939466

Regression verification flows in modern integrated circuit development environments expose a plethora of counter-examples during simulation. Sorting these counter-examples today is a tedious and time-consuming process. High level design debugging aims to triage these counter-examples into groups that will be assigned to the appropriate verification and/or design engineers for detailed root cause analysis. In this work, we present an automated triage process that leverages knowledge extracted from simulation and SAT-based debugging. We introduce novel metrics that correlate counter-examples based on the likelihood of sharing the same root cause. Triage is formulated as a pattern recognition problem and solved by hierarchical clustering techniques to generate groups of related counter-examples. Experimental results demonstrate an overall accuracy of 94% for the proposed automated triage framework, which corresponds to a 40% improvement over conventional scripting methods.

关键词： circuit CAD computability computer debugging high level synthesis integrated circuit design pattern clustering regression analysis RTL design debugging SAT-based debugging automated triage process hierarchical clustering techniques high level design debugging integrated circuit development environments pattern recognition problem register transfer level regression verification root cause analysis satisfiability guided counter-example triage scripting methods debugging Estimation Integrated circuit modeling Measurement Probabilistic logic Silicon Solid modeling

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On Enhancing the Debug Architecture of a System-on-Chip (SoC) to Detect Software Attacks 28

On Enhancing the Debug Architecture of a System-on-Chip (SoC...

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2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)

作者： Backer, Jerry Hely, David Karri, Ramesh NYU Polytech Sch Engn Brooklyn NY 11201 USA Univ Grenoble Alpes LCIS F-26000 Valence France

ISBN: (纸本)9781509003129

The prevalent use of systems-on-chip (SoCs) makes them prime targets for software attacks. Proposed security countermeasures monitor software execution in real-time, but are impractical, and require impractical changes to the internal logic of intellectual property (IP) cores. We leverage the software observability provided by the readily available SoC debug architecture to detect attacks without modifying IP cores. We add hardware components to configure the debug architecture for security monitoring, to store a golden software execution model, and to notify a trusted kernel process when an attack is detected. Our evaluations show that the additions do not impact runtime software execution, and incur 9% area and power overheads on a low-cost processor core.

关键词： computer debugging logic circuits system-on-chip IP cores SoC debug architecture enhancement area overheads attack detection hardware components intellectual property cores internal logic low-cost processor core power overheads runtime software execution security monitoring software attack detection software execution model software execution monitoring software observability trusted kernel process IP networks Instruments Monitoring Registers Software Table lookup system-on-chip safety monitoring computer software Table lookup Logic circuits Registers Internet Protocol networks execute of software debugger computer programs Intellectual Property

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Simple Models Allow Simulation and Verification Early in the Design

Simple Models Allow Simulation and Verification Early in the...

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SAE 2015 World Congress and Exhibition

作者： Price, James Mentor Graphics Corp. United States

Compressed development cycles drive increased focus on virtual development, including both functional verification and quantitative simulation of electrical system designs. However, one hurdle often cited is the effort needed to develop behavioral models of electrical components such as wires, fuses, and ECUs and time required to run simulation. This presentation shows that it is fully possible to obtain reliable and "good enough" results to aid product development using simpler models and rule based verifications. By placing these models in a re-usable library and providing a simple, visual interaction environment, early design debugging using a computer becomes possible for every electrical engineer. Copyright © 2015 SAE International.

关键词： computer debugging

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Software-Based Microprocessor Verification Methodology for Linux Booting

Software-Based Microprocessor Verification Methodology for L...

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IEEE 2nd International Symposium on Next-Generation Electronics (ISNE)

作者： Chen, Chien-Chih Yeh, Chi-Tsai Huang, Ing-Jer Natl Sun Yat Sen Univ Dept Comp Sci & Engn Kaohsiung 80424 Taiwan

ISBN: (纸本)9781467330374;9781467330367

The first program executed on the general microprocessor is the operating system (OS) to setup and initiate the necessary mechanisms like as the cache unit, interrupt, memory management unit (MMU), etc. However, OS verification is a heavy and complicate task. This paper proposes a software-based verification methodology for the microprocessor. This verification covers the whole functionalities of the Linux OS including the pipelined core, exception control unit, cache unit and MMU. The authors applies the proposed methodology to validate ARM7-like microprocessor for booting Linux. They also develop the verification generation techniques for regression test. The experimental results show that the proposed methodology detects the 47 design bugs leading to a system crash at the startup stage.

关键词： Linux cache storage computer bootstrapping computer debugging exception handling formal verification interrupts microprocessor chips

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Novel Views of Performance Data to Analyze Large-scale Adaptive Applications

Novel Views of Performance Data to Analyze Large-scale Adapt...

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25th ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis (SC)

作者： Bhatele, Abhinav Gamblin, Todd Isaacs, Katherine E. Gunney, Brian T. N. Schulz, Martin Bremer, Peer-Timo Hamann, Bernd Lawrence Livermore Natl Lab Ctr Appl Sci Comp Livermore CA 94551 USA Univ Calif Dept Comp Sci Davis CA USA

ISBN: (纸本)9781467308052;9781467308045

Performance analysis of parallel scientific codes is becoming increasingly difficult due to the rapidly growing complexity of applications and architectures. Existing tools fall short in providing intuitive views that facilitate the process of performance debugging and tuning. In this paper, we extend recent ideas of projecting and visualizing performance data for faster, more intuitive analysis of applications. We collect detailed per-level and per-phase measurements for a dynamically load-balanced, structured AMR library and project per-core data collected in the hardware domain on to the application's communication topology. We show how our projections and visualizations lead to a rapid diagnosis of and mitigation strategy for a previously elusive scaling bottleneck in the library that is hard to detect using conventional tools. Our new insights have resulted in a 22% performance improvement for a 65,536-core run of the AMR library on an IBM Blue Gene/P system.

关键词： computer debugging data analysis data visualisation mesh generation multiprocessing systems parallel processing performance evaluation

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Debug Aware AXI-based Network Interface

Debug Aware AXI-based Network Interface

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IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

作者： Neishaburi, M. H. Zilic, Zeljko McGill Univ Dept Elect Engn Montreal PQ Canada

ISBN: (纸本)9780769545561

With a significant increase in the complexity of cores and their intercommunications, there is a need to review and enhance traditional debug methods for System on Chips (SoCs). As new SoCs tend to have many cores, the interactions among cores through functional interconnects such as bus or Network on Chips (NoCs) are becoming so complex. Therefore, debug techniques should address not only validation of the computational part of a design but such techniques have to monitor and validate the communication and synchronization among cores inside SoCs. In this paper, we consider NoC as a functional interconnection among cores and propose debug aware network interface (NI) which is compatible with AXI standard. The proposed interface enables provides a mechanism for cross-trigger debugging. Transactions issued by a processing element connected to the proposed debug aware NI are monitored by the proposed cross-trigger unit and trace data and trigger events will be extracted and routed to another processing element or Shared debugging Unit (SDU). SDU combines debug traces from different processing elements. The major benefits of using our proposed architectures for debugging over traditional techniques are as follows: 1) the proposed debug aware NI can detect, mark and bypass severe faulty conditions such as deadlocks resulting from design errors or electrical faults in real time 2) there is no need for a large internal trace memory inside processing element because SDU can communicate to the external memory 3) debugging of applications which are running on multiple processors can facilitate by means of available features inside the proposed trigger mechanism.

关键词： AXI standard Debug debugging Monitoring Network Interface Network interfaces Network on Chip Nickel NoC Protocols SDU SoC System-on-a-chip computer debugging cross-trigger debugging cross-trigger unit deadlocks debug aware AXI-based network interface debu

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Backward Reasoning with Formal Properties: A methodology for bug isolation on simulation traces

Backward Reasoning with Formal Properties: A methodology for...

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20th Asian Test Symposium (ATS)

作者： Komuravelli, Anvesh Mitra, Srobona Banerjee, Ansuman Dasgupta, Pallab IIT Kharagpur Dept Comp Sc & Engg Kharagpur W Bengal India India stat Inst Adv Comp & Microelect Unit Kolkata India

ISBN: (纸本)9780769545837

Automated methods for bug localization for hardware designs typically work on the design implementation to root-cause a given bug. This paper presents a novel debugging approach where instead of using the design implementation in the debugging process, we use causal deduction using formal properties scattered across the design to locate the bug. This has two advantages, namely, (a) the reasoning takes place in the property space instead of the state space of the implementation, which enhances scalability, and (b) new properties can be added in hindsight to perform what-if analysis, which is less expensive than modifying the implementation for each alternative. Experimental results demonstrate the scalability of the approach in debugging designs with large property suites.

关键词： Algorithm design and analysis Assertions Bug localization Cognition computer bugs Cost accounting debugging Protocols Scalability Verification backward reasoning bug isolation causal deduction computer debugging debugging approach formal property formal v

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A Distributed AXI-based Platform for Post-Silicon Validation

A Distributed AXI-based Platform for Post-Silicon Validation

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29th IEEE VLSI Test Symposium (VTS)/Workshop on Design for Reliability and Variability (DRV)

作者： Neishaburi, M. H. Zilic, Zeljko McGill Univ Montreal PQ H3A 2A7 Canada

ISBN: (纸本)9781612846552

With a significant increase in the design complexity of cores and associated communication among them, post-silicon validation has become a demanding task in System on Chips (SoCs) design. To ensure that final products are fault-free and ready for market, the post-silicon validation goal is to catch bugs and pinpoint the root causes of errors that could escape from pre-silicon verification tools. Post-silicon validation involves running a hardware prototype in an environment that is similar to its final platform with its expected workload. As new SoCs tend to have many cores, the interactions among these cores are becoming so complex that post-silicon debug techniques should address not only validation of the functional aspects of a design but such techniques have to "bulletproof" the communication and synchronization among cores inside an SoC. In this paper, we propose an AXI based environment for post-silicon validation. The proposed environment involves Local debugging Unit (LDU) and Shared debugging Unit (SDU). LDU monitors trace of transactions issued by the hardware prototype and detect undesired conditions on bus. SDU combines debug traces from different LDUs. We embed the proposed SDU inside an AXI configurable interconnect. Major benefits of using our proposed debug platform over traditional techniques for silicon validation are as follows: 1) it detects and bypasses real time severe faulty conditions such as deadlocks resulting from design errors or electrical faults 2) there is no need for internal trace memory because SDU can communicate to the external memory through slave ports 3) it enables online monitoring of the trace buffer.

关键词： AXI configurable interconnect debugging Hardware Monitoring Prototypes SDRAM Si System-on-a-chip advanced extensible interface communication computer debugging design complexity distributed AXI-based platform electrical faults elemental semiconductors hardware prototype integrated circuit design integrated circuit interconnections internal trace memory local debugging unit peripheral interfaces post-silicon debug techniques post-silicon validation pre-silicon verification tools shared debugging unit silicon synchronization system on chips design system-on-chip

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New Tools For Research and Development Acceleration of GNSS Receivers

New Tools For Research and Development Acceleration of GNSS ...

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5th ESA Workshop on Satellite Navigation Technologies / European Workshop on GNSS Signals and Signal Processing (NAVITEC)

作者： Plausinaitis, Darius Borre, Kai Aalborg Univ Danish GPS Ctr Aalborg Denmark

ISBN: (纸本)9781424487417

This paper analyzes strengths and shortcomings of the existing aids for GNSS receiver development. A new set of tools is presented that provides to the developer debugging and optimization capabilities not supplied so far by existing tools. The proposed tools are simple and therefore very affordable, but never the less they are very functional. The first results are presented from the application of the proposed tools in a GNSS receiver debugging.

关键词： GNSS receivers computer debugging radio receivers receiver debugging receiver optimization research and development research and development acceleration satellite navigation

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