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NII Technical Reports 2005年第13期2005卷 1-28页

作者： Kaneiwa, Ken Satoh, Ken National Institute of Informatics 2-1-2 Hitotsubashi Chiyoda-ku Tokyo 101-8430 Japan

Automatic debugging of UML class diagrams is helpful for users to visually specify software systems because they cannot detect errors of logical inconsistency easily. This paper focuses on tractable consistency checking of UML class diagrams. We accurately identify inconsistencies in the diagrams by translating them into first-order predicate logic generalized by counting quantifiers and classify their expressivities by eliminating some components. For class diagrams of different expressive powers, we introduce optimized algorithms that compute their respective consistencies in P, NP, PSPACE, or EXPTIME with respect to the size of the class diagram. In particular, restricting the attribute value types decreases the complexities from EXPTIME to P and PSPACE for the two cases in which class diagrams contain (i) disjointness constraints and overwriting/multiple inheritances and (ii) these components together with completeness constraints. Additionally, we guarantee that there exists a meaningful restriction of class diagrams such that no logical inconsistency is caused.

关键词： computer debugging

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Assertion-based on-line verification and debug environment for complex hardware systems

Assertion-based on-line verification and debug environment f...

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IEEE International Symposium on Circuits and Systems

作者： Peterson, K Savaria, Y Ecole Polytech Dept Elect & Comp Engn Montreal PQ H3C 3A7 Canada

This paper describes a debug environment for high performance integrated circuits and systems, running in real-world conditions. With the proposed environment, debug data is collected by a built-in debug hardware module (or integrated probe) and transferred to an external debugger using a dedicated debug port. The external debugger, composed of a FPGA and a processor, uses real-time assertion-based verification techniques to ensure that the system acts according to its specifications. Dynamic changes in the probe configuration allow higher monitoring resolution of critical parts of the circuit or system and improve the use of the debug port bandwidth. This paper discusses advantages and limitations of this technique.

关键词： computer debugging

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A snapshot method to provide full visibility for functional debugging using FPGA

A snapshot method to provide full visibility for functional ...

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Proceedings of the Asian Test Symposium, ATS'04

作者： Chuang, Chin-Lung Lu, Dong-Jung Liu, Chien-Nan Jimmy Department of Electrical Engineering National Central University Taiwan

Until now, logic simulators are still the most popular verification tools. Although they can provide full controllability and observability during the verification process, the simulation speed is too slow for large amounts of input patterns. Using hardware emulation such as FPGA can have higher simulation speed. However, it is very hard to debug using this approach due to poor visibility in FPGAs. Therefore, in this paper, we propose another approach to "record" the internal behaviors of a FPGA and "replay" the interesting period of time in a software simulator. In this way, we can still have high simulation speed because most simulation efforts are still finished in FPGA. Moreover, full visibility and better debugging environment can be provided in the software simulation. The experimental results have shown the efficiency of using our approach.

关键词： computer debugging

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debugging complex counterexample of hardware system using control flow distance metrics

Debugging complex counterexample of hardware system using co...

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The 2004 47th Midwest Symposium on Circuits and Systems - Conference Proceedings

作者： Shen, Sheng Yu Qin, Ying Li, Sikun Natl. Univ. of Defense Technology ChangSha 410073 China

we propose a novel debugging technique for complex counterexample generated by model checking complex hardware system. It searches for a witness with control flow as similar as possible to a counterexample generated by model checker. Then it performs dynamic slicing on the difference between this two control flows, to obtain the set of difference that are actually relevant to the violation of assertion. There are tightly relation between this set and the actual bug. Starting from this difference set, actual bug can then be located by perform a breath-first source code checking. Experiment result shows that our approach is highly accurate.

关键词： computer debugging

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Designing Source-level Debug-for Embedded System Platform

Designing Source-level Debug-for Embedded System Platform

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The 8th International Conference on computer Supported Cooperative Work in Design(第八届计算机支持的协同工作设计国际会议)(CSCWD2004)

作者： Zhengjie Deng Zhanglong Chen Fudan University Embedded System Lab Shanghai200433

ISBN: (纸本)0780379411

During the development of the Platform forEmbedded System, it is an important problem to designthe source-level debugger. The software will be verycomplex to design if we simulate the system only throughsoftware. On the contrary, if we do it only by hardwarestep support, user will feel that they have wasted muchtime during debugging. In the article, we will raise anidea, which combine software with hardware. Based onthis idea, we will introduce HALF-SIMULATE which takecare of the designer and is faster than only usinghardware step support. We will explain the method ofdesigning the HALF-SIMULATE through analyzing theARM instruction, and then compare it with the other twomethods (only soft or only hard). In the end, we willconclude that the HALF-SIMULATE method is better.

关键词： program debugging program diagnostics program testing computer debugging embedded systems digital simulation source-level debugging embedded system platform hardware step support HALF-SIMULATE ARM instruction

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ReEnact: Using thread-level speculation mechanisms to debug data races in multithreaded codes

ReEnact: Using thread-level speculation mechanisms to debug ...

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30th Annual International Symposium on computer Architecture

作者： Prvulovic, M Torrellas, J Univ Illinois Urbana IL 61801 USA

ISBN: (纸本)0769519458

While removing software bugs consumes vast amounts of human time, hardware support for debugging in modem computers remains rudimentary. Fortunately, we show that mechanisms for Thread-Level Speculation (TLS) can be reused to boost debugging productivity. Most notably, TLS's rollback capabilities can be extended to support rolling back recent buggy execution and repeating it as many times as necessary until the bug is fully characterized. These incremental re-executions are deterministic even in multithreaded codes. Importantly, this operation can be done automatically on the fly, and is compatible with production runs. As a specific implementation of a TLS-based debugging framework, we introduce ReEnact. ReEnact targets a particularly hairy class of bugs: data races in multithreaded programs. ReEnact extends the communication monitoring mechanisms in TLS to also detect data races. It extends TLS's rollback capabilities to be able to roll back and deterministically re-execute the code with races to obtain the race signature. Finally, the signature is compared to a library of race patterns and, if a match occurs, the execution may be repaired. Overall, ReEnact successfully detects, characterizes, and often repairs races automatically on the fly. Moreover, it is fully compatible with always-on use in production runs: the slowdown of race-free execution with ReEnact is on average only 5.8%.

关键词： computer debugging

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debugging Distributed Computations by Reverse Search

Debugging Distributed Computations by Reverse Search

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21st IASTED International Multi-Conference on Applied Informatics

作者： Andrzejak, Artur Fukuda, Komei University Erlangen-Nuremberg Department of Computer Science Martensstr. 3 91058 Erlangen Germany School of Computer Science McGill University Montreal H3A 2A7 Canada

ISBN: (纸本)0889863415

We develop a memory-efficient off-line algorithm for the enumeration of global states of a distributed computation. The algorithm allows the parameterization of its memory requirements against the running time. This is particularly useful for debugging of memory-intensive parallel computations, e.g. in image processing or data warehousing. We also show how to apply our technique to evaluate in a memory-efficient way the predicate Definitely(φ) defined by Cooper, Marzullo and Neiger. The basis for these algorithms is Reverse Search, a paradigm successfully applied for enumeration of a variety of geometric objects.

关键词： computer debugging

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Self-diagnostic tools of the APEmille parallel machine

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IEE PROCEEDINGS-computerS AND DIGITAL TECHNIQUES 2002年第6期149卷 273-279页

作者： Chessa, S Errico, W Maestrini, P Sallay, B Schifano, F Tripiccione, R CNR Ist Elaboraz Informaz Area Ric I-56124 Pisa Italy Univ Pisa Dipartimento Informat I-56127 Pisa Italy Ist Nazl Fis Nucl Pisa Italy Univ Ferrara Dipartimento Fis I-44100 Ferrara Italy

The authors describe the self-diagnostic tools of the APEmille SIMD machine, whose logical architecture is a three-dimensional torus of processors. The tools are aimed at implementing system-level diagnosis using a comparison model. The diagnostic model accounts for some critical features of the APEmille architecture, and has been validated by means of VHDL simulation. Essentially, diagnostic tools force all processors to synchronously execute the same test program using the same data set, and compare the outputs of adjacent processors in real time. The diagnostic tools also implement a preliminary test session aimed at covering faults that might disrupt the comparison model. The diagnosis algorithm and the test programs used in comparison tests are also described.

关键词： parallel machines APEmille SIMD machine torus of processors Parallel architecture Multiprocessing systems self-diagnostic tools fault-tolerance diagnostic tools VHDL simulation computer debugging hardware description languages Performance evaluation and testing logical architecture fault tolerant computing Hardware-software codesign

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Extension language automation of embedded system debugging

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Automated Software Engineering 2002年第1期9卷 7-39页

作者： Parson, Dale Schlieder, Bryan Beatty, Paul Agere Systems 1247 South Cedar Crest Blvd. Allentown PA 18103 United States

Embedded systems contain several layers of target processing abstraction. These layers include electronic circuit, binary machine code, mnemonic assembly code, and high-level procedural and object-oriented abstractions. Physical and temporal constraints and artifacts within physically embedded systems make it impossible for software engineers to operate at a single layer of processor abstraction. The Luxdbg embedded system debugger exposes these layers to debugger users, and it adds an additional layer, the extension language layer, that allows users to extend both the debugger and its target processor capabilities. Tcl is Luxdbg's extension language. Luxdbg users can apply Tcl to automate interactive debugging steps, to redirect and to interconnect target processor input-output facilities, to schedule multiple processor execution, to log and to react to target processing exceptions, to automate target system testing, and to prototype new debugging features. Inclusion of an extension language like Tcl in a debugger promises additional advantages for distributed debugging, where debuggers can pass extension language expressions across computer networks.

关键词： computer debugging

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A metadebugger prototype for the HARNESS metacomputing framework

A metadebugger prototype for the HARNESS metacomputing frame...

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10th Annual IEEE International Symposium on High Performance Distributed Computing

作者： Lovas, R Sunderam, V Hungarian Acad Sci Res Inst MTA SZTAKI Comp & Automat H-1518 Budapest Hungary

In order to solve the emerging debugging issues in the field of metacomputing we defined the fundamental principles of an adaptive and integrated debugging and visualization tool: a novel metadebugger The current prot... 详细信息

ISBN: (纸本)0769512968

关键词： computer debugging

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