In the modern digital equipments, as the speed of the ASICs and the complexity of the PCBs increase, the electronic designers have to control the noise on the boards to avoid EMC and signal integrity problems. One of ...
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Xbox is Microsoft's future-generation video-game console system that has been developed using National Instruments' LabVIEW, the PXI platform, and Windows 2000. This functional test station is reliable, flexib...
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Xbox is Microsoft's future-generation video-game console system that has been developed using National Instruments' LabVIEW, the PXI platform, and Windows 2000. This functional test station is reliable, flexible, cost-effective, and easy to maintain and upgrade.
The system-on-chip (SOC) design methodologies were described for cellular products capable to interact with the Internet. The importance of SOC design methodologies was established by the IEEE-ISTO Nexus 5001 Forum. T...
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The system-on-chip (SOC) design methodologies were described for cellular products capable to interact with the Internet. The importance of SOC design methodologies was established by the IEEE-ISTO Nexus 5001 Forum. The real-time visibility problems in embedded microcontrollers were discussed with respect to complex embedded systems.
The increased clock frequencies and higher integration levels of today's high-performance embedded microcontrollers have led to the widespread incorporation of on-chip debugging logic into new microcontroller chip...
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The increased clock frequencies and higher integration levels of today's high-performance embedded microcontrollers have led to the widespread incorporation of on-chip debugging logic into new microcontroller chip designs. The newly defined standard for embedded system debugging, the IEEE-ISTO Nexus 5001 Forum Standard for a Global Embedded Debug Interface, is introduced and is related to the test and debugging requirements of development engineers.
Simulations for modern designs are often performed on Field Programmable Gate Array technology in a functional test and debugging process known as emulation, allowing for more complex simulations than possible in soft...
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ISBN:
(纸本)0780363159
Simulations for modern designs are often performed on Field Programmable Gate Array technology in a functional test and debugging process known as emulation, allowing for more complex simulations than possible in software. One drawback to emulation is the lengthy time spent in the back-end CAD tools for each debugging iteration, including debugging changes and the introduction of control and observation logic. We have developed a technique that confines the re-place-and-route area to only the portions of the design affected by the introduction of the rest logic and by the debugging changes. Therefore, the back-end CAD effort for error detection, localization, and correction is reduced. This benefit is achieved by partitioning the design at the physical level into independent blocks, and the test logic and design changes are localized to the affected blocks. The result is a shortened time between debugging iterations, and thus a shortened time-to-market for the design.
Improving debug techniques for logic failures is a constant imperative. This paper describes the results of implementing a logic mapping methodology that integrates in-line manufacturing defect data and scan-based dia...
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Improving debug techniques for logic failures is a constant imperative. This paper describes the results of implementing a logic mapping methodology that integrates in-line manufacturing defect data and scan-based diagnosis for a complex microprocessor. The correlation between the physical failure analysis results and defect inspection data is presented and analyzed. Methods to improve the percentage of 'hits' are explored, supported by a detailed account of challenges and obstacles encountered during the experiment. Finally, the paper also briefly highlights the amount of time that can be saved in process debug through the usage of logic mapping.
Symbolic debuggers are system development tools that can accelerate the validation speed of behavioral specifications by allowing a user to interact with an executing code at the source level. In response to a user qu...
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Symbolic debuggers are system development tools that can accelerate the validation speed of behavioral specifications by allowing a user to interact with an executing code at the source level. In response to a user query, the debugger retrieves the value of a source variable in a manner consistent with respect to the source statement where execution has halted. However, when a behavioral specification has been optimized using transformations, values of variables may be inaccessible in the run-time state. We have developed a set of techniques that, given a behavioral specification CDFG, enforce computation of a selected subset Vcut of user variables such that (i) all other variables v qq CDFG can be computed from Vcut and (ii) this enforcement has minimal impact on the optimization potential of the computation. The implementation of the new debugging approach poses several optimization tasks. We have formulated the optimization tasks and developed heuristics to solve them. The effectiveness of the approach has been demonstrated on a set of benchmark designs.
Throughout 1998, the High Performance debugging Forum worked on defining a base level standard for high performance debuggers. The standard had to meet the sometimes conflicting constraints of being useful to users, r...
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Throughout 1998, the High Performance debugging Forum worked on defining a base level standard for high performance debuggers. The standard had to meet the sometimes conflicting constraints of being useful to users, realistically implementable by developers, and architecturally independent across multiple platforms. To meet criteria for timeliness, the standard had to be defined in one year and in such a way that it could be implemented within an additional year. The Forum was successful, and in November 1998 released Version 1 of the HPD Standard. Implementations of the standard are currently underway. This paper presents an overview of Version 1 of the standard and an analysis of the process by which the standard was developed. The status of implementation efforts and plans for follow-on efforts are discussed as well.
This paper presents a novel hardware-based approach for identifying, profiling, and monitoring hot spots in order to support runtime optimization of general-purpose programs. The proposed approach consists of a set of...
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This paper presents a novel hardware-based approach for identifying, profiling, and monitoring hot spots in order to support runtime optimization of general-purpose programs. The proposed approach consists of a set of tightly coupled hardware tables and control logic modules that are placed in the retirement stage of a processor pipeline removed from the critical path. The features of the proposed design include rapid detection of program hot spots after changes in execution behavior, runtime-tunable selection criteria for hot spot detection, and negligible overhead during application execution. Experiments using several SPEC95 benchmarks, as well as several large WindowsNT applications, demonstrate the promise of the proposed design.
For today's multi-million transistor designs, existing design verification techniques cannot guarantee that first silicon is designed error free. Therefore, techniques are necessary to efficiently debug first-sili...
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For today's multi-million transistor designs, existing design verification techniques cannot guarantee that first silicon is designed error free. Therefore, techniques are necessary to efficiently debug first-silicon. In this article, we present a methodology for debugging multiple clock domain systems-on-a-chip. In addition to scan chains, a set of Design-for-Debug modules is designed into an IC to make it debuggable. Debugger tool software interacts with the on-chip DfD to make the debug features available from a workstation.
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