The paper examines issues associated with the concept of development of software of motion control systems intended for processing unit automation. Possible variants of hardware and software implementation of such sys...
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The paper examines issues associated with the concept of development of software of motion control systems intended for processing unit automation. Possible variants of hardware and software implementation of such systems are given. The concept for building the motion control system on the basis of automaton-based realization of logical control and motion control programs (PLC and PMC) via the virtual machine is proposed. The Forth implementation of automaton-based programming of PLC programs is demonstrated.
An introduction is presented in which the editor discusses various reports within the issue on topics including energy efficiency and autonomy, open networks and location independent human-readable identification and ...
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An introduction is presented in which the editor discusses various reports within the issue on topics including energy efficiency and autonomy, open networks and location independent human-readable identification and device-independent application development facilities.
We designed an algorithm and software for inverse kinetic problem solving by conditional global minimization of the deviation of calculated data from experimental data. This approach allows use of more complete inform...
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We designed an algorithm and software for inverse kinetic problem solving by conditional global minimization of the deviation of calculated data from experimental data. This approach allows use of more complete information on the process, which narrows the region of feasibility and increases the quality of mathematical simulation of chemical reactions. The algorithms designed were tested in the kinetic description of a complex liquid-phase chain reaction, specifically, the oxidation of n-decane in the presence of an inhibiting composition, viz., para-oxydiphenylamine + n-decanol.
Seeking to improve information integration throughout the manufacturing *** MATERIALS AVAILABLE FOR DOWNLOAD Buy this article Html (20KB)PDF (1.18MB)Digital Edition
Seeking to improve information integration throughout the manufacturing *** MATERIALS AVAILABLE FOR DOWNLOAD Buy this article Html (20KB)PDF (1.18MB)Digital Edition
ECOA is an active software architecture research programme conducted by the French Republic and United Kingdom. It is one product of the recent Defence and Security Co-operation Treaty signed between the two nations. ...
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ECOA is an active software architecture research programme conducted by the French Republic and United Kingdom. It is one product of the recent Defence and Security Co-operation Treaty signed between the two nations. This paper provides an overview of the programme goals and progress as well as an introduction to the technology being developed and comparison to related initiatives. The goal of the ECOA programme is to define an open software architecture that enables collaborative development of mission system software. The ECOA programme is needed to reduce development and lifecycle costs of future military air programmes. For this reason the programme has a specific focus on combat-air mission systems but the underlying technology is general purpose, applying to multiple military and civil At present, the programme has defined a concept, delivered a set of initial technical standards and produced a joint demonstrator to validate the technology developed.
Requirements engineering is an important part of the softwaredevelopment process. There are various challenges associated with the elicitation, analysis, documentation, and validation of requirements, and these chall...
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Requirements engineering is an important part of the softwaredevelopment process. There are various challenges associated with the elicitation, analysis, documentation, and validation of requirements, and these challenges can be more pronounced in embedded software systems, where a number of characteristics, unique to these systems, must be addressed. This paper will examine the unique concerns surrounding the requirements engineering of embedded software systems, including the need to elicit, specify, and validate, interrupts and exceptions, concurrency, and timing. We will then survey and examine some of the current requirements engineering research that can address these concerns. Finally, we will consider whether some of the requirements engineering concerns and practices conceived for, and utilized in the Information Technology (IT) domain, can be beneficial to the development of embedded systems.
As software (SW) becomes more and more an important aspect of embedded system development, project schedules are requiring the earlier development of software simultaneously with hardware (HW). In addition, verificati...
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As software (SW) becomes more and more an important aspect of embedded system development, project schedules are requiring the earlier development of software simultaneously with hardware (HW). In addition, verification has increasingly challenged the design of complex mixed-signal SoC products. This is exacerbated for automotive safety critical SoC products with a high number of analogue interfaces (sensors and actuators) to the physical components such as an airbag SoC chipset. Generally, it is widely accepted that verification accounts for around 70% of the total SoC development. Since integration of HW and SW is the most crucial step in embedded system development, the sooner it is done, the sooner verification can begin. As such, any approaches which could allow verification and integration of HW/SW to be deployed earlier in the development process and help to decrease verification effort, (e.g.: accelerate verification runs) are of extreme interest. In the described context, this paper addresses not only the design and verification challenges of such embedded systems but also proposes a new development, verification and validation workflow using an FPGA-based SoC Emulation System with synthesizable analogue functional stubs and a risk minimizing analogue test chip, which emulates and partially implements respective mixed-signal behavior of the ASIC SoC hardware. The workflow can also be called FPGA-in-the-Loop (FiL) and it is proven to help multi-disciplinary development teams to vastly improve the quality of HW/SW co-design at system level with as little time and effort as possible.
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