Portable, efficient, parallel programming requires cost models to compare different possible implementations. In turn, these require knowledge of the shapes of the data structures being used, as well as knowledge of t...
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Portable, efficient, parallel programming requires cost models to compare different possible implementations. In turn, these require knowledge of the shapes of the data structures being used, as well as knowledge of the hardware parameters. This paper shows how shape analysis techniques developed in the FISh programming language could be exploited to produce a data parallel language with an accurate, portable cost model. (C) 2000 Elsevier Science B.V. All rights reserved.
In this paper, a new method of evaluation for information system project is proposed on the basis of the meta-synthesis methodology from qualitative analysis to quantitative analysis. DHGF is an integrated method of i...
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In this paper, a new method of evaluation for information system project is proposed on the basis of the meta-synthesis methodology from qualitative analysis to quantitative analysis. DHGF is an integrated method of improved Delphi, analytic hierarchy process, grey interconnect degree and fuzzy comprehensive evaluating. It gives full play to their advantages and controls theirs disadvantages. The feasibility and effectiveness of DHGF are shown in the practical example.
In practice, a pure top-down and refinement-based development process is not applicable. A more iterative and incremental approach is usually applied with respect to changing requirements. We call such an approach an ...
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In practice, a pure top-down and refinement-based development process is not applicable. A more iterative and incremental approach is usually applied with respect to changing requirements. We call such an approach an evolutionary approach. As existing methodologies rely on refinement concepts they do not support an evolutionary development. In this paper, we present the basic concepts of a suitable overall methodology based on componentware and software evolution. We clarify the difference between refinement steps and evolution steps in a document-based development methodology. We propose an evolutionary development process during system design. To support this process at the best, we need to be able to model and track the dependencies between the various development documents. Currently there is no adequate modeling technique available. To close this gap, we introduce the concept of Requirements/Assurances Contracts. These contracts could be rechecked whenever the specification of a component evolves. This allows the impacts of that evolutionary step to be determined. Developers are able to track and manage the software evolution process. A short example shows the usefulness of the presented concepts and introduces a description technique for requirements/assurances contracts in componentware.
This paper describes the characterization of a synthetic workload for performance evaluation of a new system before replacing a legacy system. The workload is used by CAPPLES, a capacity planning and performance analy...
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This paper describes the characterization of a synthetic workload for performance evaluation of a new system before replacing a legacy system. The workload is used by CAPPLES, a capacity planning and performance analysis method for the migration of legacy systems. Typical workload characterization problems are anticipated and discussed. Further, guidelines to characterize a CAPPLES workload for different migration scenarios are provided.
The analysis of assembly code to provide a high level control flow view in terms of the usual high level looping and selection constructs is of great assistance to high level language programmers who are attempting to...
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The analysis of assembly code to provide a high level control flow view in terms of the usual high level looping and selection constructs is of great assistance to high level language programmers who are attempting to understand and port low-level code as part of a system re-engineering project. This paper describes the control flow analyzer component of our asm21toc reverse compiler from assembly language programs for the ADSP-21xx family of Digital Signal Processors to ANSI-C. We give a brief overview of the class of processors and programs that we have studied so as to motivate the design of our reverse compiler. We describe the merged call-graph/dataflow representation that supports our analyses and the way in which hierarchical structural control flow information is extracted and stored. We give summary statistics showing the usage of various classes of control flow structure along with occurrences of non-disjoint functions, self modifying code and non-reducible control flow constructs.
This paper presents a technique for recovering the high level design of legacy software systems according to user defined architectural plans. Architectural plans are represented using a description language and speci...
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This paper presents a technique for recovering the high level design of legacy software systems according to user defined architectural plans. Architectural plans are represented using a description language and specify system components and their interfaces. Such descriptions are viewed as queries that are applied on a large data base which stores information extracted from the source code of the subject legacy system. Data mining techniques and a modified branch and bound search algorithm are used to control the matching process, by which the query is satisfied and query variables are instantiated. The matching process allows the alternative results to be ranked according to data mining associations and clustering techniques and, finally, be presented to the user.
Given an input sequence of data, a motif is a repeating pattern, possibly interspersed with "dont care" characters. The data could be a sequence of characters or sets of characters or even real values. In th...
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ISBN:
(纸本)0898714532
Given an input sequence of data, a motif is a repeating pattern, possibly interspersed with "dont care" characters. The data could be a sequence of characters or sets of characters or even real values. In the first two cases: the number of motifs could potentially be exponential in the size of the input sequence and in the third case there could be infinite number of motifs (assuming two real numbers are equal if they are within some specified delta > 0 of each other). However. it has been shown in some motif based applications, such as multiple sequence alignment [Par98, PFR99], that a small subset of these motifs capture all the relevant information. Also, from an information-theoretic viewpoint, the special motifs represent the sets with low co-relation, hence of higher informational value. In this paper, we show, for any sequence with n characters, there exists only a linear (or no more than 3n) number of these special motifs and every other motif can be constructed from this set. We term these special motifs as irredundant motifs. We also present an efficient polynomial time algorithm to generate these motifs. This bound on the number of useful motifs gives validation to motif-based approaches, since the total number of irredundant motifs does not explode. This result is potentially of significance to most applications that use pattern discovery as the basic engine such as data mining, clustering, matching and others.
This work adopts a psychologically motivated evaluative framework in the comparison of a visual and a textual programming language. The framework used is a formal interpretation of "cognitive dimensions", fo...
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ISBN:
(纸本)0769508405
This work adopts a psychologically motivated evaluative framework in the comparison of a visual and a textual programming language. The framework used is a formal interpretation of "cognitive dimensions", focusing upon the notion of notation viscosity. In contrast to many studies of visual languages, we do not primarily focus upon programs, but on program modification. Hence, a program (visual or textual) is viewed as an artifact which is manipluated by programmers. Thus in general the question addressed is one of how do visual and textual languages differ in terms of the artifact which programmers interactively manipulate. More specifically, we are able to demonstrate the use of an evaluative framework in the comparative assessment of visual and textual programming languages.
In designing complex systems, a performance evaluation model is essential in determining a system configuration and identifying performance bottlenecks. Several C++-based general-purpose simulation tools such as syste...
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ISBN:
(纸本)076950728X
In designing complex systems, a performance evaluation model is essential in determining a system configuration and identifying performance bottlenecks. Several C++-based general-purpose simulation tools such as systemC and CynLib have also been introduced. However, these tools are cycle-based, which simulates a system synchronously under the assumption that all modules are invoked even cycle, thus eliminating scheduling overhead in order;to simulate a system containing multiple clocks or asynchronous circuits with accuracy, an event-driven approach is highly desirable. We have developed an event-driven framework of computer system simulation in C++, called simCore, which is mainly targeted for performance evaluation simulation of computersystems, providing concurrent execution of multiple modules and event-driven module interaction mechanisms. However, in order to demonstrate its cycle-accuracy and high simulation speed, rye compared two MIPS-based system simulators, one bused on the C++-based event-driven simulation core and the other based on Verilog-XL.
This paper describes a methodology for developing processor specific tools such as assemblers, disassemblers, processor simulators, compilers etc., using processor models in a generic way. The processor models are wri...
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ISBN:
(纸本)0769506682
This paper describes a methodology for developing processor specific tools such as assemblers, disassemblers, processor simulators, compilers etc., using processor models in a generic way. The processor models are written in a language called Sim-nML [1] which is powerful enough to capture the instruction set architecture of a processor. We describe a few tools in this paper which can be retargeted to any processor using the high level Sim-nML model of the processor.
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