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An open-source, efficient and parameterizable hardware implementation of the AES algorithm 12

An open-source, efficient and parameterizable hardware imple...

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12th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA)

作者： Nacci, A. A. Rana, V. Sciuto, D. Santambrogio, M. D. Politecn Milan DEIB I-20133 Milan Italy

ISBN: (纸本)9781479942930

Although the reliability and robustness of the AES protocol have been deeply proved through the years, recent research results and technology advancements are rising serious concerns about its solidity in the (quite near) future. In this context, we are proposing an extension of the AES algorithm in order to support longer encryption keys (thus increasing the security of the algorithm itself). In addition to this, we are proposing a set of parametric implementations of this novel extended protocols. These architectures can be optimized either to minimize the area usage or to maximize their performance. Experimental results show that, while the proposed implementations achieve a throughput higher than most of the state-of-the-art approaches and the highest value of the Performance Area metric when working with 128-bit encryption keys, they can achieve a 84x throughput speed-up when compared to the approaches that can be found in literature working with 512-bit encryption keys.

关键词： computerarchitecture Encryption Fieldprogrammablegatearrays Protocols Quantumcomputing Standards Throughput cryptography Throughput protocols AES gene Auger electron spectroscopy Keys Keys Locks Cays Soundness open source

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Kernel-User Space Separation in DRAM Memory 12

Kernel-User Space Separation in DRAM Memory

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12th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA)

作者： Li, Xi Sun, Beilei Zhu, Zongwei Wang, Chao Zhou, Xuehai Univ Sci & Technol China Suzhou Inst Adv Study Suzhou Peoples R China Univ Sci & Technol China Dept Comp Sci Hefei 230027 Peoples R China

ISBN: (纸本)9781479942930

Performance of software is increasingly restricted by the Memory Wall instead of CPU. Many studies focus on alleviating the DRAM latency by improving the row-buffer hit rate. But most of them treat the Kernel(1) and User(2) equally. Data used by Operating System and User applications spread in different rows of the same bank, leading to the contentions for the row-buffer when they access the bank successively. We find that contentions between Kernel and User make up of a great proportion of all the row-buffer misses. To alleviate the contentions between Kernel and User, we divide the united DRAM memory space into Kernel-Space and User-Space. A new page-allocation-system, the K/U-Aware page-allocation-system, is proposed to manage Kernel-Space and User-Space in DRAM memory in different address mapping schemes of DRAM memory controller. In the new system, pages are allocated from different spaces according to applicants (Kernel or User). Sizes of the two spaces increase and decrease dynamically as required. For benchmarks in PARSEC suites, the proposed system reduces the contentions of Kernel and User effectively, producing significant improvements of row-buffer hit rate. The execution time is reduced by 9.45% (max. 20.45%) and 6.51% (max. 18.05%) respectively in two typical address mapping schemes.

关键词： Benchmarktesting computerarchitecture Computers Educationalinstitutions Kernel Randomaccessmemory Switches DRAM Row-BufferHit User DRAM1 gene Kernel Seeds Consumers Switches Computers Disputes address mapping

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Low Complexity Multidimensional CDF 5/3 DWT Architecture 9

Low Complexity Multidimensional CDF 5/3 DWT Architecture

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9th International Symposium on Communication Systems, Networks & Digital Signal Processing (CSNDSP)

作者： Al-Azawi, Saad Abbas, Yasir Amer Jidin, Razali Diyala Univ Coll Engn Baquba Diyala Iraq Univ Tenaga Nas Kajang Selangor Malaysia

ISBN: (纸本)9781479925810

This paper introduces an efficient low complexity multidimensional DWT architecture. The proposed architecture is based on a lifting-scheme for the Cohen-Daubechies-Feauveau (CDF) 5/3 DWT filter. It consists of low complexity identical computation and control units which can be used easily to implement 2-D and 3-D DWT architectures. The synthesis results show that the output latency is 2N+2 clock cycles, with N-2+2N+2 clock cycles required for the first level 2-D CDF 5/3 DWT computation. The architecture is parameterized to tackle various images and wordlength sizes. Furthermore, the proposed architecture is implemented using a Virtex 6 Xilinx FPGA platform. The implementation results reveal that the proposed architecture can operate at up to 198 MHz operating frequency. This reduces the time for first level DWT decomposition of a 512x512-pixel image to less than 1.3 m sec.

关键词： Complexitytheory computerarchitecture Delays Discretewavelettransforms Hardware Imagecoding Computer hardware ARCHITECTURE CAF protocol CORE DAMAGE FREQUENCY Building construction delay control unit clock cycle MULTIDIMENSIONAL

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iCHAT: Inter-Cache Hardware-Assistant Data Transfer for Heterogeneous Chip Multiprocessors 9

<i>i</i>CHAT: Inter-Cache Hardware-Assistant Data Transfer f...

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9th IEEE International Conference on Networking, Architecture, and Storage (NAS)

作者： Gu, Junli Beckmann, Bradford M. Cao, Ting Hu, Yu Australian Natl Univ Canberra ACT 0200 Australia Chinese Acad Sci Inst Comp Technol State Key Lab Comp Architecture Beijing 100864 Peoples R China

ISBN: (纸本)9781479940875

Modern heterogeneous multiprocessors integrate CPU and GPU together to provide a boost to computational performance. Data sharing and communication between CPU and GPU has been a critical issue for the final speedup. With tighter integration of CPU and GPU, it has the advantage of sharing and moving data more efficiently in order to leverage the computational power that a GPU can provide. Initially, DMA or PCIe devices were used to transfer data between CPU and GPU with low efficiency and little flexibility. Recently a single address space and coherent cache hierarchies are being adopted in heterogeneous architectures to share data more efficiently. Thus it poses new challenge to understand the communication overheads in this new context and to improve communication efficiencies for these architectures. This paper proposes a novel approach called iCHAT (inter-Cache Hardware-Assistant data Transfer) to manage data transfer between the CPU cache and the GPU cache efficiently. The iCHAT technique proposed in this paper detects the communication patterns and eagerly evicts data from the owner's caches and prepares for the requestor's demand. We implement the iCHAT design in a simulator based on gem5 and an AMD in-house GPU simulator. Experimental results show that the communication related eviction traffic is reduced by an average of 40% and the total directory traffic is reduced by 8% on average. We implement a bounding experiment that provides a quantitative evaluation of inter CPU-GPU transfers and requests to communication data, which indicates that iCHAT could achieve on average 1.4x speedup for Rodinia benchmark suite and 1.2x speedup for AMD SDK APPs.

关键词： Benchmarktesting Coherence computerarchitecture Datatransfer Detectors Graphicsprocessingunits Hardware central processing units GRAPPER PICK UP Graphics Processing Unit Computer hardware coherence Communication Research data transmission Multiprocessor address space Speeding

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Behavior Gaps and Relations between Operating System and Applications on Accessing DRAM 19

Behavior Gaps and Relations between Operating System and App...

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19th International Conference on Engineering of Complex Computer Systems (ICECCS)

作者： Sun, Beilei Li, Xi Zhu, Zongwei Zhou, Xuehai Univ Sci & Technol China Suzhou Inst Adv Study Suzhou Peoples R China USTC Dept Comp Sci & Technol Hefei 230027 Peoples R China

ISBN: (纸本)9781479954827

Detailed analyses of the behaviors of operating system and applications are significant for taking full advantage of the precious hardware resources and improving performance. This paper focus on their DRAM access behaviors based on access proportion and row-buffer miss ratio (RBM). The access proportions of Kernel1 and User2 vary greatly in different stages throughout the lifetime of a process. Most of the row-buffer misses are caused by the one having higher access proportion. By analyzing the RBM series through ARMA model, we found that User's DRAM accesses only have short-term influences on its behavior, while the Kernel's influences are relatively deeper. The ARMA model for the RBM series is able to predict the future RBMs, which are profound basis to schedule the DRAM access commands. The results of Gaussian Fitting show that Kernel and User are tightly correlated on accessing DRAM, especially in the steady stage and the end stage of a process's life cycle. Based on this close relation, it is possible to estimate the DRAM access behaviors of the other one according to the one whose behaviors have been known. System-calls that obviously affect the access proportions and RBMs are also revealed in this paper.

关键词： Benchmarktesting computerarchitecture Computers Correlation Kernel Randomaccessmemory DRAM RBM User DRAM1 gene Kernel Operating systems Consumers Seeds Computers Access

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MICROCONTROLLER BASED MAXIMUM POWER POINT TRACKING THROUGH FCC AND MLP NEURAL NETWORKS 6

MICROCONTROLLER BASED MAXIMUM POWER POINT TRACKING THROUGH F...

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6th European Embedded Design in Education and Research Conference (EDERC)

作者： Lozito, Gabriele Maria Bozzoli, Ludovica Salvini, Alessandro Univ Rome Tre Dipartimento Ingn I-00146 Rome Italy

ISBN: (纸本)9781479968435

This paper covers the study towards the implementation of a Neural Network based approach for the efficiency control of Photovoltaic systems. The algorithm aims to track the maximum power point for the PV device whenever abrupt changes in climatic conditions occur. The core of the algorithm is a Neural Network (NN) trained by using a suitable mathematical model of the photovoltaic device. Different NN architectures and several optimization solutions were studied to investigate the best approach in terms of computational efficiency, memory footprint and prediction accuracy. The best found architecture has been implemented and tested on the microcontroller unit LM4F120H5QR by Texas Instruments by using a prototype board to drive the operating point of a low-power solar cell.

关键词： Artificialneuralnetworks computerarchitecture FCC Microcontrollers Neurons Temperaturemeasurement Microcontrollers Federal Communications Commission (FCC) maximum power point trackers efficiency control Neural network Neurons Photovoltaic systems CSRP3 gene Workstations

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A Business Strategy in the Lithium-Ion Battery Industry

A Business Strategy in the Lithium-Ion Battery Industry

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Portland International Conference on Management of Engineering & Technology (PICMET)

作者： Yamazaki, Nobuo Kubo, Hiroshi Chiba Inst Technol Dept Management & Syst Engn Chiba 2760016 Japan

ISBN: (纸本)9781890843298

Recently, modularization has progressed, particularly in the electronics industry and is receiving considerable attention. This development of modularization can be explained using the business architecture concept. Based on architecture-based strategies that add some perspectives from organizational capability and the ability development environment to this concept, many industrial studies have been developed from automobile and electronics industries. This strategic idea includes the perspective of "analytical strategies" in strategic management. However, it may be recognized that actual business operations include activities that relate to the "process", and this strategic idea includes less perspective of "process", to be utilized to develop a business strategy from the analytical result. In this paper, citing the lithium-ion battery industry as an example, architecture-based strategies was reconsidered from the strategic management perspective and their relationship was identified. Moreover, a strategic approach that also includes a process perspective was proposed from the result and its validity was examined by making a concrete proposal of a business strategy for Japanese lithium-ion battery manufacturers.

关键词： Anodes Batteries Cathodes Companies computerarchitecture Materials

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MULTICHANNEL AIRBORNE ULTRASONIC RANGING SYSTEM BASED ON THE PICCOLO C2000 MCU 6

MULTICHANNEL AIRBORNE ULTRASONIC RANGING SYSTEM BASED ON THE...

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6th European Embedded Design in Education and Research Conference (EDERC)

作者： Cambini, C. Giuseppi, L. Calzolai, M. Giannelli, P. Capineri, L. Univ Florence Italy Dept Informat Engn I-50139 Florence Italy

ISBN: (纸本)9781479968435

The combination of different characteristics of airborne ultrasonic transducers for ranging applications opens up new applications for autonomous navigation systems in robotics. The features of a Piccolo C2000 MCV are suitable for the design of a ranging system with four channels. Each channel has different operating range and accuracy depending on the transducer characteristics and the implemented ranging technique. This paper presents the system architecture and the experimental results obtained with transducers operating at 40kHz, 100kHz and 300kHz.

关键词： Abstracts computerarchitecture Distancemeasurement Education Navigation Robots Transducers Transducers Robot navigation Education Piccolos range measurement system micro-controller unit MCU gene ultrasonic ranging Navigation systems airborne Building systems

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Multi-agent Pre-trade Analysis Acceleration in FPGA

Multi-agent Pre-trade Analysis Acceleration in FPGA

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IEEE Conference on Computational Intelligence for Financial Engineering and Economics (CIFEr)

作者： Gerlein, Eduardo McGinnity, T. M. Belatreche, Ammar Coleman, Sonya Li, Yuhua Univ Ulster Coleraine BT52 1SA Londonderry North Ireland

ISBN: (纸本)9781479923809

Electronic trading in global markets and exchanges requires sophisticated communication and data management systems. Novel computational infrastructures and trading strategies are required to support the massive amount of incoming streaming data, where the main problem is in latency management. Multi-agent Systems have been recognized as a promising solution to address complex problems in many areas such as biology, social sciences and financial markets and may provide powerful and flexible solutions for implementing trading engines. In addition, reconfigurable hardware based on Field Programmable Gate Arrays (FPGAs) offers many important performance benefits over software implementations, such as reducing decision making latency and high-throughput data processing. Robust and scalable trading engines can be developed by leveraging the benefits of reconfigurable FPGA platforms. This paper presents a multi-agent architecture in reconfigurable hardware for financial applications and the implementation of a trading engine for pre-trade analysis as a validation scenario. Performance results show that calculation of technical indicators and trading strategy evaluation to generate trading signals with a latency of 550 ns is achievable.

关键词： computerarchitecture Engines Fieldprogrammablegatearrays Hardware Multi-agentsystems Portfolios Ports(Computers) Engines Field programmable gate arrays Computer hardware BRIEFCASE reconfigurable hardware Latency data management systems

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Concepts and Requirements for a Cloud-based Optimization Service

Concepts and Requirements for a Cloud-based Optimization Ser...

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2nd Asia-Pacific Conference on the Computer Aided System Engineering (APCASE)

作者： Kurschl, Werner Pimminger, Sebastian Wagner, Stefan Heinzelreiter, Johann Univ Appl Sci Upper Austria Sch Informat Commun & Media A-4232 Hagenberg Austria

ISBN: (纸本)9781479945689

Cloud computing has gained widespread acceptance in both the scientific and commercial community. Mathematical optimization is one of the domains, which benefit from cloud computing by using additional computing power for optimization problems to reduce the calculation time. Of course this is also true for our field of metaheuristic optimization. Metaheuristics provide powerful methods to solve a wide range of optimization problems and may be used as a foundation for a data analysis service. Due to the deficiency of an agreed-upon reference architecture it is quit cumbersome to compare existing solutions regarding different kinds of aspects (e.g. scalability, custom extensions, workflow, etc.). Besides the usual user working with an optimization service we also have those who are responsible for architecting and implementing these systems. The lack of a list of requirements and any formal reference architecture makes it even harder to improve those systems. For that reason we have raised the following questions: i) what are the requirements, ii) what are the commonalities of existing optimization software, and iii) can we deduce a reference architecture for a cloud-based optimization service? This paper presents a comprehensive analysis of current research projects and important requirements in the context of optimization services, which then leads to the definition of a reference architecture and forms the base of any further evaluation. We also present our own hybrid cloud-based optimization service (OaaS), which is built upon the PaaS-approach of Windows Azure. OaaS defines a generic and extensible service which can be adapted to support custom optimization scenarios.

关键词： Algorithmdesignandanalysis Cloudcomputing computerarchitecture Dataanalysis Optimization Servers Servers Cloud Computing computational time Building construction ARCHITECTURE

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