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***:: Experiences with a pervasive computing architecture

IEEE PERVASIVE computing 2004年第3期3卷 22-30页

作者： Grimm, R NYU New York NY USA

A new architecture, ***, provides an integrated, comprehensive framework for building pervasive applications. It targets applications that automatically adapt to highly dynamic computing environments, and it includes services that make it easier for developers to manage constant change. We illustrate the metrics for designing and evaluating pervasive computing systems. The performance measurements are done using Sun's Java Hotspot virtual machine.

关键词： computing architecture One World Pervasive Applications Dynamic computing Discovery Migration Asynchronous Events Tuples

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Lane Shared Bit-Pragmatic Deep Neural Network computing architecture and Circuit

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2021年第1期68卷 486-490页

作者： Yang, Shaofei Liu, Longjun Li, Yingxiang Li, Xinxin Sun, Hongbin Zheng, Nanning Xi An Jiao Tong Univ Coll Artificial Intelligence Fac Elect & Informat Engn Xian 710049 Peoples R China

It is critical to continously improve the hardware efficiency of deep neural network accelerators for its application on resource constrained platform. This brief proposes a lane shared bit-pragmatic architecture to address the synchronization induced performance bottleneck and hence further improve the performance and efficiency of bit-serial computing architecture. The effectiveness and efficiency of the proposed architecture are demonstrated by extensive evaluation results.

关键词： Computer architecture Synchronization Microsoft Windows Computational modeling Registers Neural networks Random access memory Deep neural network computing architecture activation bit-sparsity synchronization efficiency

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Evolution of grid computing architecture and grid adoption models

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IBM SYSTEMS JOURNAL 2004年第4期43卷 624-645页

作者： Joseph, J Ernest, M Fellenstein, C IBM Global Serv Integrated Technol Serv Gaithersburg MD 20879 USA IBM Global Serv Strateg Outsourcing Brookfield CT 06804 USA

During recent years, we have witnessed a major paradigm shift in distributed computing principles, with a focus towards service orientation, open standards integration, collaboration, and virtualization. One particular area of interest centers on the evolution of grid computing principles into the mainstream of distributed computing and Web services. In this paper, we focus our analysis on this evolution and the significance of achieving some form of standardization of grid-computing architecture principles. This paper presents the technology standards that are driving major grid initiatives and explains in simple terms how these standards and technologies are aligned with the IBM on demand business concepts. In addition, we discuss the recent Web services specifications related to stateful resources (i.e., resources whose behavior is defined with respect to their underlying state) and how these standards relate to grid computing. We conclude with discussions exploring major aspects of grid-computing adoption models and some significant attributes that influence the transformation, collaboration, and virtualization features of these models.

关键词： .Web Services cations Virtualization Resource Sharing distributed computing open standards Distributed Systems Evolution of grid computing architecture grid adoption IBM Global IBM on demand

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RRAM-Based In-Memory computing architecture Designs

RRAM-Based In-Memory Computing Architecture Designs

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作者： Wang, Xinxin University of Michigan

学位级别：Ph.D., Doctor of Philosophy

New computing applications, e.g., deep neural network (DNN) training and inference, have been a driving force that changed the semiconductor industry landscape. The data-intensive nature of DNN applications usually leads to high computation costs and complexity, and different hardware accelerators have thus been developed to improve the efficiency of running these models. For example, NVIDIA GPU, google TPU and near-memory computing architectures can enhance DNN performance (inferences/second) and energy efficiency (TOPS/W) compared to conventional CPUs. Past that, IMC methods can circumvent the fundamental von Neumann bottleneck and enable highly parallel computing, and will lead to even higher hardware efficiency and performance. In this thesis, we examine several aspects of IMC accelerators based on emerging memory devices such as RRAM, which can potentially offer high computation density, throughput and energy efficiency. To start, we present an IMC design that is reconfigurable and can accelerate general arithmetic and logic functions. The system consists of small look-up tables (LUTs), a memory block, and search auxiliary blocks, all implemented in the same RRAM crossbar array. External data access and data conversions are eliminated to allow operations fully in-memory. Details of logic and arithmetic functions such as addition, AND and multiplication operations are discussed on the basis of search and writeback steps. A compact instruction set is demonstrated in this architecture through circuit-level simulations. Performance evaluations show that the proposed IMC architecture is suitable for handling data-intensive tasks with very low power consumption. Next, we discuss DNN accelerator designs using a tiled IMC architecture. Popular models including VGG-16 and MobileNet are successfully mapped and tested on the RRAM-based tiled IMC architecture. Effects of finite RRAM array size and quantized partial sums (Psums) due to ADC precision constraints are analyzed

关键词： computing architecture Deep neural network Hardware system Spiking Neural Network Binary activations

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Test and Development Bench for an In-borne computing architecture

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IFAC Proceedings Volumes 1990年第2期23卷 15-18页

作者： J. Bancelin H. Bordenave RATP. 13 rue Jules Valles. 75011 Paris. France

The RATP (Rail) Rolling Stock Department set in motion a whole range of investigations, research projects and experiments in 1982 aimed at defining a computing architecture for future rolling stock. The present article describes the methods and means deployed for evaluating the computing architecture and in-borne local networks for MF 88 and MP 89 rolling stock scheduled for introduction on the RATP Metro System as from 1991.

关键词： computing architecture Reconfiguration Local networks

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AI-OBC: Conceptual Design of a Deep Neural Network based Next Generation Onboard computing architecture for Satellite Systems

AI-OBC: Conceptual Design of a Deep Neural Network based Nex...

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首届中国微小卫星大会

作者： Rashedul Huq Monirul Islam Shahnewaz Siddique Dept.of ECE North South University

The latest developments in embedded processing and hardware based low powered artificial intelligence(AI) accelerators employing Deep Neural Network(DNN) have not been implemented in existing real-time computing architecture designs for Nano and microsatellites. The objective of this paper is to present a new conceptual design for a real time Deep Learning based on-board computing architecture, which has an onboard Software Defined Radio(SDR) and a low powered Deep Learning module. The concept presented in this paper simplifies the interfacing between the different modules and is power efficient. AI-OBC will achieve these additional AI and image-processing operations by combining high performance commercial off-the-shelf(COTS) hardware components with the latest hardware based low powered AI accelerators and SDR.

关键词： Artificial Intelligence computing architecture Deep Neural Network Satellite Systems Software Defined Radio Embedded Systems CubeSat Space Protocol

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A Readout System for High-Speed CCD Cameras Based on Advanced Telecommunications computing architecture

A Readout System for High-Speed CCD Cameras Based on Advance...

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IEEE Nuclear Science Symposium and Medical Imaging Conference

作者： Patrick McVittie Devis Contarato Peter Denes Dionisio Doering John Joseph John Weizeorick Lawrence Berkeley National Laboratory One Cyclotron Rd. MS50A6134 Berkeley CA 94720 USA Argonne National Laboratory Argonne IL USA

ISBN: (纸本)9781467320283

This paper describes the performance of a scalable readout system for high-speed CCD sensors based on the Advanced Telecommunication computing architecture specification. The paper reports the readout system performance tested with a IMPixel Frame Store CCD sensor for soft X-ray applications at synchrotron light sources. This camera is capable of producing image data at over 400 MB/s which must be processed in real-time and stored to disk. The high-level hardware architecture, signal processing data flow, and network protocol optimization are also be presented.

关键词： CCD computing architecture Cameras Based

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Scalable Mixed-Criticality Safety Concepts for a Stationary Battery Management System (BMS) With Integrated Machine Learning (ML)

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IEEE ACCESS 2025年 13卷 59811-59825页

作者： Arraztoa-Lazkanotegi, Xabier Marcos, David Garmendia, Maitane Olasagasti, Enaut Muxika Perez-Cerrolaza, Jon Basque Res & Technol Alliance BRTA Ikerlan Technol Res Ctr Arrasate Mondragon 20500 Spain Mondragon Unibertsitatea Dept Elect & Comp Sci Arrasate Mondragon 20500 Spain

Battery management systems (BMSs) play a crucial role in controlling and supervising the safe operation of lithium-ion batteries in stationary energy storage systems. The integration of mixed-criticality functions (combining safety functions of different criticality and non-safety-related functions) into these electronic embedded systems offers significant potential benefits but also introduces technical and certification challenges. Additionally, modern BMSs are increasingly integrating battery models based on machine learning (ML). This publication contributes with the example-based design and analysis of scalable computing architectures for the development of a mixed-criticality BMS that integrates ML battery models in stationary applications. The safety concept focuses on the computing architecture, where mixed-criticality functions and ML models are integrated, and on analyzing the advantages and disadvantages of the proposed approaches. The computing architectures discussed range from widely used lockstep and single-core processor solutions to high-performance computing platforms such as multicore devices. The system-on-a-chip with hypervisor is identified as the preferred architecture for a BMS that is flexible to efficiently adapt and integrate non-safety-related functions that require intensive computing resources without compromising safety requirements.

关键词： Safety Computer architecture Computational modeling Standards Multicore processing IEC Standards Lithium-ion batteries Certification Maximum likelihood estimation Machine learning Battery management systems (BMS) lithium-ion batteries machine learning (ML) stationary energy storage systems computing architecture multicore processing functional safety

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Design and implementation of a synchronous Hardware Performance Monitor fora RISC-V space-oriented processor

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MICROPROCESSORS AND MICROSYSTEMS 2025年 112卷

作者： Arribas, Miguel Jimenez Hellin, Agustin Martinez Mateo, Manuel Prieto del Rio, Ivan Gamino Gallego, Andrea Fernandez Polo, oscar Rodriguez da Silva, Antonio Parra, Pablo Sanchez, Sebastian Univ Alcala Space Res Grp Alcala De Henares 28805 Madrid Spain

The ability to collect statistics about the execution of a program within a CPU is of the utmost importance across all fields of computing since it allows characterizing the timing performance of a program. This capability is even more relevant in safety-critical software systems, where it is mandatory to analyze the software timing requirements to ensure the correct operation of the programs. Moreover, in order to properly evaluate and verify the extra-functional properties of these systems, besides timing performance, there are many other statistics available on a CPU, such as those associated with its resource utilization. In this paper, we showcase a Performance Measurement Unit (PMU), also known as a Hardware Performance Monitor (HPM), integrated into a RISC-V On-Board Computer (OBC) designed for space applications by our research group. The monitoring technique features a novel approach whereby the events triggered are not counted immediately but instead are propagated through the pipeline so that their annotation is synchronized with the executed instruction. Additionally, we also demonstrate the use of this PMU in a process to characterize the execution model of the processor. Finally, as an example of the statistics provided by the PMU, the results obtained running the CoreMark and Dhrystone benchmarks on the RISC-V OBC are shown.

关键词： Performance counters Performance measuring unit RISC-V computing architecture On-board computing

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Hybrid architecture for Handwriting Perceptual Service based on Edge computing 13

Hybrid Architecture for Handwriting Perceptual Service based...

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13th IEEE International Conference on Services computing (SCC) / 13th IEEE International Conference on Web Services (ICWS)

作者： Su, Tonghua Wen, Huiyan Zhang, Mingyue Liu, Shuchen Wang, Zhongjie Xu, Xiaofei Harbin Inst Technol Sch Software Harbin Peoples R China

ISBN: (纸本)9781728187891

Handwriting is a natural way to express idea and perceptual service of daily handwriting is in great need. However, current cloud computing paradigm suffers from slow response, excessive networking bandwidth surge and vulnerable security. We propose a hybrid computing architecture incorporating edge computing and wireless sensor network to deliver handwriting perceptual service. Instead of uploading all raw data to the cloud, we offload the handwriting detection and text recognition services to the edge devices. Most bandwidth can be saved. The edge devices are organized to form wireless sensor networks, which possesses high resilience to disasters or damages. Merely the semantic texts than handwritten images are submitted to the cloud and resultant prompts or decisions are sent back. Our computing architecture in general has a fast edge intelligence response with balanced energy utilization. We implement a specific case study to investigate its feasibility. The result show that our design works pretty well.

关键词： service delivery computing architecture edge computing wireless sensing network handwriting perception

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