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IEEE International Conference on Rebooting computing (ICRC)

作者： Akyel, Kaya Can Charles, Henri-Pierre Mottin, Julien Giraud, Bastien Suraci, Gregory Thuries, Sebastien Noel, Jean-Philippe CEA LETI MINATEC Campus F-38054 Grenoble France Univ Grenoble Alpes F-38000 Grenoble France

ISBN: (纸本)9781509013708

This paper presents a novel energy-efficient and Dynamically Reconfigurable computing Circuit (DRC2) concept based on memory architecture for data-intensive (imaging, ...) and secure (cryptography, ...) applications. The proposed computing circuit is based on a 10-Transistor (10T) 3-Port SRAM bitcell array driven by a peripheral circuitry enabling all basic operations that can be traditionally performed by an ALU. As a result, logic and arithmetic operations can be entirely executed within the memory unit leading to a significant reduction in power consumption related to the data transfer between memories and computing units. Moreover, the proposed computing circuit can perform extremely-parallel operations enabling the processing of large volume of data. A test case based on image processing application and using the saturating increment function is analytically modeled to compare conventional and DRC2-based approaches. It is demonstrated that DRC2-based approach provides a reduction of clock cycle number of up to 2x. Finally, potential applications and must-be-considered changes at different design levels are discussed.

关键词： in-memory computing computing architecture programmable logic

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architecture of computing System based on Chiplet

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MICROMACHINES 2022年第2期13卷 205-205页

作者： Shan, Guangbao Zheng, Yanwen Xing, Chaoyang Chen, Dongdong Li, Guoliang Yang, Yintang Xidian Univ Sch Microelect Xian 710071 Peoples R China Beijing Inst Aerosp Control Devices Beijing 100039 Peoples R China

computing systems are widely used in medical diagnosis, climate prediction, autonomous vehicles, etc. As the key part of electronics, the performance of computing systems is crucial in the intellectualization of the equipment. The conflict between performance, efficiency, and cost can be solved by choosing an appropriate computing system architecture. In order to provide useful advice and instructions for the designers to fabricate high-performance computing systems, this paper reviews the Chiplet-based computing system architectures, including computing architecture and memory architecture. Firstly, the computing architecture used for high-performance computing, mobile, and PC is presented and summarized. Secondly, the memory architecture based on mainstream memory and emerging non-volatile memory used for data storing and processing are introduced, and the key parameters of memory are compared and discussed. Finally, this paper is concluded, and the future perspectives of computing system architecture based on Chiplet are presented.

关键词： computing system computing architecture memory architecture Chiplet

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Brain-Inspired computing: A Systematic Survey and Future Trends

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PROCEEDINGS OF THE IEEE 2024年第6期112卷 544-584页

作者： Li, Guoqi Deng, Lei Tang, Huajin Pan, Gang Tian, Yonghong Roy, Kaushik Maass, Wolfgang Chinese Acad Sci Inst Automat Beijing 100045 Peoples R China Chinese Acad Sci Key Lab Brain Cognit & Brain Inspired Intelligence Beijing 100190 Peoples R China Peng Cheng Lab Shenzhen 518055 Peoples R China Tsinghua Univ Dept Precis Instrument Beijing 100084 Peoples R China Zhejiang Univ Coll Comp Sci & Technol MOE Frontier Sci Ctr Brain Sci & Brain Machine Int State Key Lab Brain Machine Intelligence Hangzhou 310027 Peoples R China Peking Univ Dept Comp Sci Beijing 100091 Peoples R China Purdue Univ Sch Elect & Comp Engn W Lafayette IN 47907 USA Graz Univ Technol Sch Comp Sci A-8010 Graz Austria

Brain-inspired computing (BIC) is an emerging research field that aims to build fundamental theories, models, hardware architectures, and application systems toward more general artificial intelligence (AI) by learning from the information processing mechanisms or structures/functions of biological nervous systems. It is regarded as one of the most promising research directions for future intelligent computing in the post-Moore era. In the past few years, various new schemes in this field have sprung up to explore more general AI. These works are quite divergent in the aspects of modeling/algorithm, software tool, hardware platform, and benchmark data since BIC is an interdisciplinary field that consists of many different domains, including computational neuroscience, AI, computer science, statistical physics, material science, and microelectronics. This situation greatly impedes researchers from obtaining a clear picture and getting started in the right way. Hence, there is an urgent requirement to do a comprehensive survey in this field to help correctly recognize and analyze such bewildering methodologies. What are the key issues to enhance the development of BIC? What roles do the current mainstream technologies play in the general framework of BIC? Which techniques are truly useful in real-world applications? These questions largely remain open. To address the above issues, in this survey, we first clarify the biggest challenge of BIC: how can AI models benefit from the recent advancements in computational neuroscience? With this challenge in mind, we will focus on discussing the concept of BIC and summarize four components of BIC infrastructure development: 1) modeling/algorithm;2) hardware platform;3) software tool;and 4) benchmark data. For each component, we will summarize its recent progress, main challenges to resolve, and future trends. Based on these studies, we present a general framework for the real-world applications of BIC systems, which is promisi

关键词： Artificial intelligence Hardware Benchmark datasets brain-inspired computing (BIC) computing architecture neuromorphic chips neuromorphic sensors software tool spiking neural networks (SNNs) computing architecture neuromorphic chips neuromorphic sensors software tool spiking neural networks (SNNs)

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Factors that Determine the Adoption of Cloud computing: A Global Perspective

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INTERNATIONAL JOURNAL OF ENTERPRISE INFORMATION SYSTEMS 2010年第4期6卷 55-68页

作者： Arinze, Bay Anandarajan, Murugan Drexel Univ Management Informat Syst Philadelphia PA 19104 USA Drexel Univ Dept Management Management Informat Syst Philadelphia PA 19104 USA

Cloud computing has spread within enterprise faster than many other IT innovations. In cloud computing, computer services are accessed over the Internet in a scalable fashion, where the user is abstracted in varying degrees from the actual hardware and software and pays only for resources used. This paper examines the adoption of cloud computing in various regions of the world, as well as the potential of cloud computing to impact computing in developing countries. The authors propose that cloud computing offers varying benefits and appears differently in regions across the world, enabling many users to obtain sophisticated computing architectures and applications that are cost-prohibitive to acquire locally. The authors examine issues of privacy, security, and reliability of cloud computing and discuss the outlook for firms and individuals in both developing and developed countries seeking to utilize cloud computing for their computing needs.

关键词： Cloud computing computing architecture Developing Countries Enterprise computing IT Infrastructure Software as a Service

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Configurable 8T SRAM for Enbling in-Memory computing 2

Configurable 8T SRAM for Enbling in-Memory Computing

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2nd International Conference on Communication Engineering and Technology (ICCET)

作者： Chen, Han-Chun Li, Jin-Fu Hsu, Chun-Lung Sun, Chi-Tien Natl Cent Univ Dept Elect Engn Taoyuan 320 Taiwan Ind Technol Res Inst Informat & Commun Res Labs Hsinchu 300 Taiwan

ISBN: (纸本)9781728114392

To cope with the memory wall of von-Neumann computing architecture, the in-memory-computing (IMC) architecture has been proposed. The IMC architecture embeds logic into the memory array to reduce the data transfer between the processor and memory. This paper proposes a configurable 8T SRAM which can provide the functions of ternary content address memory, left shift, and right shift in addition to the storage function. The method only needs to modify the peripheral circuitry of an 8T SRAM. The Hspice simulator is used to verify configurable 8T SRAM using TSMC 0.18 mu m CMOS technology.

关键词： in-memory computing static random access memory content addressable memory computing architecture

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FedECS: Client Selection for Optimizing computing Energy in Federated Learning 34

FedECS: Client Selection for Optimizing Computing Energy in ...

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IEEE 34th Annual International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC)

作者： Han, Shuo Zhang, Chenyu Wang, Luhan Zheng, Wei Wen, Xiangming Beijing Univ Post & Telecommun Beijing Lab Adv Informat Networks Beijing Peoples R China

ISBN: (纸本)9781665464833

With the rapid development of artificial intelligence, computing energy consumption has become a research focus. Due to privacy protection, it is difficult to exchange data between participants, which leads to repeated training of the same model for different clients. This paper aims to reduce the computing energy consumption caused by repeated training of the same model. This paper first proves the effect of Federated Learning (FL) on lowering computing energy consumption. Then considering the client computing architecture, this paper proposes an FL algorithm for the energy-efficiency-ratio-based client selection (FedECS). The proposed algorithm reduces the total energy consumption of FL through the trade-off of iteration rounds and energy consumption per round. In addition, this paper performs extensive simulations, including different data partitions and computing architecture distributions. Experiments show that compared with the FedAvg algorithm, the proposed algorithm can reduce energy consumption by 17.2% similar to 48.2%.

关键词： Data silos energy computing architecture federated learning client selection

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Area-Delay Efficient and Low-Power Carry Skip Adder for High Performance computing Systems 5

Area-Delay Efficient and Low-Power Carry Skip Adder for High...

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5th IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)

作者： Patel, Sujit Kumar Garg, Bharat Mahajan, Anurag Rai, Shireesh Kumar Thapar Inst Engn & Technol Patiala ECE Dept Patiala Punjab India Symbiosis Int Deemed Univ Symbiosis Inst Technol E&TC Dept Pune Maharashtra India

ISBN: (纸本)9781728146553

The high performance computing architectures are the primary need for the modern devices having compute-intensive applications such as signal and image processing. This paper presents a novel low complexity carry-skip adder design that provides high-speed and consumes low-power making it suitable for the development of high-performance signal processing cores. The proposed adder is derived from the reformulated Boolean expressions that avoid the redundant computations with reduced critical path delay. The proposed architectures are coded in VHDL and synthesized with Synopsys Design Compiler using 65nm CMOS library. Synthesis results demonstrate that the proposed 32-bit carry skip adder reduces the delay, area and power by 10.2%, 13.6% and 8% respectively than the best known carry skip adder. Finally, the proposed 16- and 32-bit adders reduce the area-delay product by 14.4% and 22.5% respectively over the existing adder.

关键词： Carry-Skip adder Low-power High-speed computing architecture Logic complexity

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Airborne computing Platform Based Joint Offload and Deployment Optimization Algorithm 19

Airborne Computing Platform Based Joint Offload and Deployme...

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19th IEEE International Wireless Communications and Mobile computing (IEEE IWCMC)

作者： Wang, Jie Liu, Lei Xie, Weiliang China Telecom Res Inst Mobile Commun Res Dept Beijing Peoples R China

ISBN: (纸本)9798350333398

Communication capabilities are a fundamental need to establish a future 6G integrated space-air-ground communication system. 6G computing networks must provide high-performance computing platforms with limited resources, and will in the future include network nodes such as constellation satellites and high-altitude platforms. This paper first assesses the need for an integrated air-space communication system and the main technical difficulties of networking. Then the space-ground integrated 6G computing architecture is explained. This is followed by an in-depth discussion of the system model, which includes a communication model, a computational model, and an energy model. Finally, we describe the FedDCO approach in detail and focus on the integrated optimization of computational offloading and airborne platform deployment in a multi-user scenario. Simulation results show that the FedDCO approach can significantly improve the model convergence speed and solve the airborne platform deployment and computational offloading problems.

关键词： space-air-ground network computing capability scheduling aerial platform computing computing architecture

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ENAS oriented layer adaptive data scheduling strategy for resource limited hardware

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NEUROcomputing 2020年第0期381卷 29-39页

作者： Li, Chuxi Fan, Xiaoya Geng, Yuling Yang, Zhao Wang, Danghui Zhang, Meng Northwestern Polytech Univ Minist Educ Sch Comp Sci Engn & Res Ctr Embedded Syst Integrat Xian 710129 Peoples R China

Efficient Neural architecture Search (ENAS) is an effective solution for building deep Convolutional Neural Network (CNN) models automatically. However, it is confronted with challenges when concerning deploying the searched networks on embedded platforms under limited resources. The key issue is the mismatch between the traditional data scheduling and the irregularity of layers from ENAS searched networks, which results in remarkable bandwidth pressure increment, and further leads to performance degradation and power consumption increase. In this paper, three alternative data scheduling patterns are constructed for different layers from ENAS searched networks, and a layer adaptive data scheduling strategy is proposed according to the constrained resources given by embedded platforms. Additionally, an adaptive architecture is also presented to deploy the searched networks efficiently, providing 4-10x performance speedup and 2.5-6x power consumption saving. (C) 2019 Elsevier B.V. All rights reserved.

关键词： Efficient neural architecture search Resource limited hardware Hardware deployment computing architecture Data scheduling strategy

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Design of a Portable Cluster Supercomputer for Particle Image Velocimetry Data Processing

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JOURNAL OF AEROSPACE computing INFORMATION AND COMMUNICATION 2008年第11期5卷 448-459页

作者： Hauser, Thomas Perl, Mark A. Utah State Univ Logan UT 84322 USA

In this paper, we present the design of a portable cluster supercomputer created specifically for processing particle image velocimetry image data. To make this computer system portable for a laboratory environment, it is designed to run on minimal power, to be lightweight, and portable. The hardware configuration consists of 12 processing nodes with a total of 48 processor cores, one master node with five terabytes of disk storage, and a gigabit ethernet interconnect. The total configuration along with a rugged transportation case has an approximate gross weight of 390 lb and works on one standard 120V, 20A electric circuit. With this cluster computer, a speedup of 28 relative to standard serial processing of a large particle image velocimetry data set was achieved.

关键词： Supercomputers Particle Image Velocimetry Data Processing computing architecture Data Acquisition System Electric Power Experimental Fluid Dynamics Direct Numerical Simulation Parallel computing Operating Systems

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