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作者： Wang, Xinxin University of Michigan

学位级别：Ph.D., Doctor of Philosophy

New computing applications, e.g., deep neural network (DNN) training and inference, have been a driving force that changed the semiconductor industry landscape. The data-intensive nature of DNN applications usually leads to high computation costs and complexity, and different hardware accelerators have thus been developed to improve the efficiency of running these models. For example, NVIDIA GPU, google TPU and near-memory computing architectures can enhance DNN performance (inferences/second) and energy efficiency (TOPS/W) compared to conventional CPUs. Past that, IMC methods can circumvent the fundamental von Neumann bottleneck and enable highly parallel computing, and will lead to even higher hardware efficiency and performance. In this thesis, we examine several aspects of IMC accelerators based on emerging memory devices such as RRAM, which can potentially offer high computation density, throughput and energy efficiency. To start, we present an IMC design that is reconfigurable and can accelerate general arithmetic and logic functions. The system consists of small look-up tables (LUTs), a memory block, and search auxiliary blocks, all implemented in the same RRAM crossbar array. External data access and data conversions are eliminated to allow operations fully in-memory. Details of logic and arithmetic functions such as addition, AND and multiplication operations are discussed on the basis of search and writeback steps. A compact instruction set is demonstrated in this architecture through circuit-level simulations. Performance evaluations show that the proposed IMC architecture is suitable for handling data-intensive tasks with very low power consumption. Next, we discuss DNN accelerator designs using a tiled IMC architecture. Popular models including VGG-16 and MobileNet are successfully mapped and tested on the RRAM-based tiled IMC architecture. Effects of finite RRAM array size and quantized partial sums (Psums) due to ADC precision constraints are analyzed

关键词： computing architecture Deep neural network Hardware system Spiking Neural Network Binary activations

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Lane Shared Bit-Pragmatic Deep Neural Network computing architecture and Circuit

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2021年第1期68卷 486-490页

作者： Yang, Shaofei Liu, Longjun Li, Yingxiang Li, Xinxin Sun, Hongbin Zheng, Nanning Xi An Jiao Tong Univ Coll Artificial Intelligence Fac Elect & Informat Engn Xian 710049 Peoples R China

It is critical to continously improve the hardware efficiency of deep neural network accelerators for its application on resource constrained platform. This brief proposes a lane shared bit-pragmatic architecture to address the synchronization induced performance bottleneck and hence further improve the performance and efficiency of bit-serial computing architecture. The effectiveness and efficiency of the proposed architecture are demonstrated by extensive evaluation results.

关键词： Computer architecture Synchronization Microsoft Windows Computational modeling Registers Neural networks Random access memory Deep neural network computing architecture activation bit-sparsity synchronization efficiency

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AI-OBC: Conceptual Design of a Deep Neural Network based Next Generation Onboard computing architecture for Satellite Systems

AI-OBC: Conceptual Design of a Deep Neural Network based Nex...

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首届中国微小卫星大会

作者： Rashedul Huq Monirul Islam Shahnewaz Siddique Dept.of ECE North South University

The latest developments in embedded processing and hardware based low powered artificial intelligence(AI) accelerators employing Deep Neural Network(DNN) have not been implemented in existing real-time computing architecture designs for Nano and microsatellites. The objective of this paper is to present a new conceptual design for a real time Deep Learning based on-board computing architecture, which has an onboard Software Defined Radio(SDR) and a low powered Deep Learning module. The concept presented in this paper simplifies the interfacing between the different modules and is power efficient. AI-OBC will achieve these additional AI and image-processing operations by combining high performance commercial off-the-shelf(COTS) hardware components with the latest hardware based low powered AI accelerators and SDR.

关键词： Artificial Intelligence computing architecture Deep Neural Network Satellite Systems Software Defined Radio Embedded Systems CubeSat Space Protocol

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Brain-Inspired computing: A Systematic Survey and Future Trends

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PROCEEDINGS OF THE IEEE 2024年第6期112卷 544-584页

作者： Li, Guoqi Deng, Lei Tang, Huajin Pan, Gang Tian, Yonghong Roy, Kaushik Maass, Wolfgang Chinese Acad Sci Inst Automat Beijing 100045 Peoples R China Chinese Acad Sci Key Lab Brain Cognit & Brain Inspired Intelligence Beijing 100190 Peoples R China Peng Cheng Lab Shenzhen 518055 Peoples R China Tsinghua Univ Dept Precis Instrument Beijing 100084 Peoples R China Zhejiang Univ Coll Comp Sci & Technol MOE Frontier Sci Ctr Brain Sci & Brain Machine Int State Key Lab Brain Machine Intelligence Hangzhou 310027 Peoples R China Peking Univ Dept Comp Sci Beijing 100091 Peoples R China Purdue Univ Sch Elect & Comp Engn W Lafayette IN 47907 USA Graz Univ Technol Sch Comp Sci A-8010 Graz Austria

Brain-inspired computing (BIC) is an emerging research field that aims to build fundamental theories, models, hardware architectures, and application systems toward more general artificial intelligence (AI) by learning from the information processing mechanisms or structures/functions of biological nervous systems. It is regarded as one of the most promising research directions for future intelligent computing in the post-Moore era. In the past few years, various new schemes in this field have sprung up to explore more general AI. These works are quite divergent in the aspects of modeling/algorithm, software tool, hardware platform, and benchmark data since BIC is an interdisciplinary field that consists of many different domains, including computational neuroscience, AI, computer science, statistical physics, material science, and microelectronics. This situation greatly impedes researchers from obtaining a clear picture and getting started in the right way. Hence, there is an urgent requirement to do a comprehensive survey in this field to help correctly recognize and analyze such bewildering methodologies. What are the key issues to enhance the development of BIC? What roles do the current mainstream technologies play in the general framework of BIC? Which techniques are truly useful in real-world applications? These questions largely remain open. To address the above issues, in this survey, we first clarify the biggest challenge of BIC: how can AI models benefit from the recent advancements in computational neuroscience? With this challenge in mind, we will focus on discussing the concept of BIC and summarize four components of BIC infrastructure development: 1) modeling/algorithm;2) hardware platform;3) software tool;and 4) benchmark data. For each component, we will summarize its recent progress, main challenges to resolve, and future trends. Based on these studies, we present a general framework for the real-world applications of BIC systems, which is promisi

关键词： Artificial intelligence Hardware Benchmark datasets brain-inspired computing (BIC) computing architecture neuromorphic chips neuromorphic sensors software tool spiking neural networks (SNNs) computing architecture neuromorphic chips neuromorphic sensors software tool spiking neural networks (SNNs)

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architecture of computing System based on Chiplet

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MICROMACHINES 2022年第2期13卷 205-205页

作者： Shan, Guangbao Zheng, Yanwen Xing, Chaoyang Chen, Dongdong Li, Guoliang Yang, Yintang Xidian Univ Sch Microelect Xian 710071 Peoples R China Beijing Inst Aerosp Control Devices Beijing 100039 Peoples R China

computing systems are widely used in medical diagnosis, climate prediction, autonomous vehicles, etc. As the key part of electronics, the performance of computing systems is crucial in the intellectualization of the equipment. The conflict between performance, efficiency, and cost can be solved by choosing an appropriate computing system architecture. In order to provide useful advice and instructions for the designers to fabricate high-performance computing systems, this paper reviews the Chiplet-based computing system architectures, including computing architecture and memory architecture. Firstly, the computing architecture used for high-performance computing, mobile, and PC is presented and summarized. Secondly, the memory architecture based on mainstream memory and emerging non-volatile memory used for data storing and processing are introduced, and the key parameters of memory are compared and discussed. Finally, this paper is concluded, and the future perspectives of computing system architecture based on Chiplet are presented.

关键词： computing system computing architecture memory architecture Chiplet

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Scalable Mixed-Criticality Safety Concepts for a Stationary Battery Management System (BMS) With Integrated Machine Learning (ML)

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IEEE ACCESS 2025年 13卷 59811-59825页

作者： Arraztoa-Lazkanotegi, Xabier Marcos, David Garmendia, Maitane Olasagasti, Enaut Muxika Perez-Cerrolaza, Jon Basque Res & Technol Alliance BRTA Ikerlan Technol Res Ctr Arrasate Mondragon 20500 Spain Mondragon Unibertsitatea Dept Elect & Comp Sci Arrasate Mondragon 20500 Spain

Battery management systems (BMSs) play a crucial role in controlling and supervising the safe operation of lithium-ion batteries in stationary energy storage systems. The integration of mixed-criticality functions (combining safety functions of different criticality and non-safety-related functions) into these electronic embedded systems offers significant potential benefits but also introduces technical and certification challenges. Additionally, modern BMSs are increasingly integrating battery models based on machine learning (ML). This publication contributes with the example-based design and analysis of scalable computing architectures for the development of a mixed-criticality BMS that integrates ML battery models in stationary applications. The safety concept focuses on the computing architecture, where mixed-criticality functions and ML models are integrated, and on analyzing the advantages and disadvantages of the proposed approaches. The computing architectures discussed range from widely used lockstep and single-core processor solutions to high-performance computing platforms such as multicore devices. The system-on-a-chip with hypervisor is identified as the preferred architecture for a BMS that is flexible to efficiently adapt and integrate non-safety-related functions that require intensive computing resources without compromising safety requirements.

关键词： Safety Computer architecture Computational modeling Standards Multicore processing IEC Standards Lithium-ion batteries Certification Maximum likelihood estimation Machine learning Battery management systems (BMS) lithium-ion batteries machine learning (ML) stationary energy storage systems computing architecture multicore processing functional safety

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Design and implementation of a synchronous Hardware Performance Monitor fora RISC-V space-oriented processor

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MICROPROCESSORS AND MICROSYSTEMS 2025年 112卷

作者： Arribas, Miguel Jimenez Hellin, Agustin Martinez Mateo, Manuel Prieto del Rio, Ivan Gamino Gallego, Andrea Fernandez Polo, oscar Rodriguez da Silva, Antonio Parra, Pablo Sanchez, Sebastian Univ Alcala Space Res Grp Alcala De Henares 28805 Madrid Spain

The ability to collect statistics about the execution of a program within a CPU is of the utmost importance across all fields of computing since it allows characterizing the timing performance of a program. This capability is even more relevant in safety-critical software systems, where it is mandatory to analyze the software timing requirements to ensure the correct operation of the programs. Moreover, in order to properly evaluate and verify the extra-functional properties of these systems, besides timing performance, there are many other statistics available on a CPU, such as those associated with its resource utilization. In this paper, we showcase a Performance Measurement Unit (PMU), also known as a Hardware Performance Monitor (HPM), integrated into a RISC-V On-Board Computer (OBC) designed for space applications by our research group. The monitoring technique features a novel approach whereby the events triggered are not counted immediately but instead are propagated through the pipeline so that their annotation is synchronized with the executed instruction. Additionally, we also demonstrate the use of this PMU in a process to characterize the execution model of the processor. Finally, as an example of the statistics provided by the PMU, the results obtained running the CoreMark and Dhrystone benchmarks on the RISC-V OBC are shown.

关键词： Performance counters Performance measuring unit RISC-V computing architecture On-board computing

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FedECS: Client Selection for Optimizing computing Energy in Federated Learning 34

FedECS: Client Selection for Optimizing Computing Energy in ...

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IEEE 34th Annual International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC)

作者： Han, Shuo Zhang, Chenyu Wang, Luhan Zheng, Wei Wen, Xiangming Beijing Univ Post & Telecommun Beijing Lab Adv Informat Networks Beijing Peoples R China

ISBN: (纸本)9781665464833

With the rapid development of artificial intelligence, computing energy consumption has become a research focus. Due to privacy protection, it is difficult to exchange data between participants, which leads to repeated training of the same model for different clients. This paper aims to reduce the computing energy consumption caused by repeated training of the same model. This paper first proves the effect of Federated Learning (FL) on lowering computing energy consumption. Then considering the client computing architecture, this paper proposes an FL algorithm for the energy-efficiency-ratio-based client selection (FedECS). The proposed algorithm reduces the total energy consumption of FL through the trade-off of iteration rounds and energy consumption per round. In addition, this paper performs extensive simulations, including different data partitions and computing architecture distributions. Experiments show that compared with the FedAvg algorithm, the proposed algorithm can reduce energy consumption by 17.2% similar to 48.2%.

关键词： Data silos energy computing architecture federated learning client selection

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Airborne computing Platform Based Joint Offload and Deployment Optimization Algorithm 19

Airborne Computing Platform Based Joint Offload and Deployme...

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19th IEEE International Wireless Communications and Mobile computing (IEEE IWCMC)

作者： Wang, Jie Liu, Lei Xie, Weiliang China Telecom Res Inst Mobile Commun Res Dept Beijing Peoples R China

ISBN: (纸本)9798350333398

Communication capabilities are a fundamental need to establish a future 6G integrated space-air-ground communication system. 6G computing networks must provide high-performance computing platforms with limited resources, and will in the future include network nodes such as constellation satellites and high-altitude platforms. This paper first assesses the need for an integrated air-space communication system and the main technical difficulties of networking. Then the space-ground integrated 6G computing architecture is explained. This is followed by an in-depth discussion of the system model, which includes a communication model, a computational model, and an energy model. Finally, we describe the FedDCO approach in detail and focus on the integrated optimization of computational offloading and airborne platform deployment in a multi-user scenario. Simulation results show that the FedDCO approach can significantly improve the model convergence speed and solve the airborne platform deployment and computational offloading problems.

关键词： space-air-ground network computing capability scheduling aerial platform computing computing architecture

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Hybrid architecture for Handwriting Perceptual Service based on Edge computing 13

Hybrid Architecture for Handwriting Perceptual Service based...

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13th IEEE International Conference on Services computing (SCC) / 13th IEEE International Conference on Web Services (ICWS)

作者： Su, Tonghua Wen, Huiyan Zhang, Mingyue Liu, Shuchen Wang, Zhongjie Xu, Xiaofei Harbin Inst Technol Sch Software Harbin Peoples R China

ISBN: (纸本)9781728187891

Handwriting is a natural way to express idea and perceptual service of daily handwriting is in great need. However, current cloud computing paradigm suffers from slow response, excessive networking bandwidth surge and vulnerable security. We propose a hybrid computing architecture incorporating edge computing and wireless sensor network to deliver handwriting perceptual service. Instead of uploading all raw data to the cloud, we offload the handwriting detection and text recognition services to the edge devices. Most bandwidth can be saved. The edge devices are organized to form wireless sensor networks, which possesses high resilience to disasters or damages. Merely the semantic texts than handwritten images are submitted to the cloud and resultant prompts or decisions are sent back. Our computing architecture in general has a fast edge intelligence response with balanced energy utilization. We implement a specific case study to investigate its feasibility. The result show that our design works pretty well.

关键词： service delivery computing architecture edge computing wireless sensing network handwriting perception

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