检索结果-内蒙古大学图书馆

23rd IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

作者： Reis, Dayane Niemier, Michael Hu, X. Sharon Univ Notre Dame Notre Dame IN 46556 USA

ISBN: (纸本)9781450357043

Data transfer between a processor and memory frequently represents a bottleneck with respect to improving application-level performance. computing in memory (CiM), where logic and arithmetic operations are performed in memory, could significantly reduce both energy consumption and computational overheads associated with data transfer. Compact, low-power, and fast CiM designs could ultimately lead to improved application-level performance. This paper introduces a CiM architecture based on ferroelectric field effect transistors (FeFETs). The CiM design can serve as a general purpose, random access memory (RAM), and can also per-form Boolean operations ((N)AND, (N)OR, X(N)OR, INV) as well as addition (ADD) between words in memory. Unlike existing CiM designs based on other emerging technologies, FeFET-CiM accomplishes the aforementioned operations via a single current reference in the sense amplifier, which leads to more compact designs and lower power. Furthermore, the high I-on/I-off ratio of FeFETs enables an inexpensive voltage-based sense scheme. Simulation-based case studies suggest that our FeFET-CiM can achieve speed-ups (and energy reduction) of similar to 119X (similar to 1.6X) and similar to 1.97X (similar to 1.5X) over ReRAM and STT-RAM CiM designs with respect to in-memory addition of 32-bit words. Furthermore, our approach offers an average speedup of similar to 2.5X and energy reduction of similar to 1.7X when compared to a conventional (not in-memory) approach across a wide range of benchmarks.

关键词： computing in memory Emerging technologies FeFETs

来源：评论

学校读者我要写书评

暂无评论

Reconfigurable Bit-Serial Operation Using Toggle SOT-MRAM for High-Performance computing in memory Architecture

引用

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2022年第11期69卷 4535-4545页

作者： Wang, Jinkai Bai, Yining Wang, Hongyu Hao, Zuolei Wang, Guanda Zhang, Kun Zhang, Youguang Lv, Weifeng Zhang, Yue Beihang Univ Fert Beijing Inst Sch Comp Sci & Engn State Key Lab Software Dev Environm Beijing 100191 Peoples R China Beihang Univ Fert Beijing Inst Sch Comp Sci & Engn MIIT Key Lab Spintron Beijing 100191 Peoples R China Beihang Univ Fert Beijing Inst Sch Integrated Circuit Sci & Engn MIIT Key Lab Spintron Beijing 100191 Peoples R China Beihang Univ Sch Comp Sci & Engn State Key Lab Software Dev Environm Beijing 100191 Peoples R China Beihang Univ Res Inst Shenzhen Key Lab Data Vitalizat Smart City Shenzhen 518057 Peoples R China Beihang Univ Hefei Innovat Res Inst Nanoelect Sci & Technol Ctr Hefei 230013 Peoples R China

computing in memory (CIM) is a promising candidate for high throughput and energy-efficient data-driven applications, which mitigates the well-known memory bottleneck in Von Neumann architecture. In this paper, we present a reconfigurable bit-serial operation using toggle spin-orbit torque magnetic random access memory (TSOT-MRAM) to perform the computation completely in the bit-cell array instead of in a peripheral circuit. This bit-serial CIM (BSCIM) scheme achieves higher throughput and energy efficiency in CIM. First, basic Boolean logic operations are realized by utilizing the feature of TSOT device. A bit-cell array that implements the bit-serial operation is then built to provide the communication between column and row necessary for arithmetic operations, such as the carry propagation of addition and multiplication. Finally, we analyze the reliability of BSCIM scheme and demonstrate the performance advantage by performing convolution operations for 28 x 28 handwritten digit images in a BSCIM architecture. The results show that the delay and energy of BSCIM architecture are respectively reduced by 1.16-5.49 times and 1.12-1.43 times compared with the existing digital CIM architectures. Besides, its throughput and energy efficiency are also enhanced to 51.2 GOPS and 9.9 TOPS/W respectively.

关键词： computing in memory bit-serial operation toggle spin-orbit torque MRAM convolution operation digital CIM architectures

来源：评论

学校读者我要写书评

暂无评论

Time-Domain computing in memory Using Spintronics for Energy-Efficient Convolutional Neural Network

引用

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2021年第3期68卷 1193-1205页

作者： Zhang, Yue Wang, Jinkai Lian, Chenyu Bai, Yining Wang, Guanda Zhang, Zhizhong Zheng, Zhenyi Chen, Lei Zhang, Kun Sirakoulis, Georgios Zhang, Youguang Beihang Univ MITT Key Lab Spintron Sch Integrated Circuit Sci Fert Beijing Inst Beijing 100191 Peoples R China Beihang Univ Hefei Innovat Res Inst Nanoelect Sci & Technol Ctr Hefei 230013 Peoples R China Democritus Univ Thrace Dept Elect & Comp Engn Xanthi 67100 Greece

The data transfer bottleneck in Von Neumann architecture owing to the separation between processor and memory hinders the development of high-performance computing. The computing in memory (CIM) concept is widely considered as a promising solution for overcoming this issue. In this article, we present a time-domain CIM (TD-CIM) scheme using spintronics, which can be applied to construct the energy-efficient convolutional neural network (CNN). Basic Boolean logic operations are implemented through recording the bit-line output at different moments. A multi-addend addition mechanism is then introduced based on the TD-CIM circuit, which can eliminate the cascaded full adders. To further optimize the compatibility of TD-CIM circuit for CNN, we also propose a quantization method that transforms floating-point parameters of pre-trained CNN models into fixed-point parameters. Finally, we build a TD-CIM architecture integrating with a highly reconfigurable array of field-free spin-orbit torque magnetic random access memory (SOT-MRAM) and evaluate its benefits for the quantized CNN. By performing digit recognition with the MNIST dataset, we find that the delay and energy are respectively reduced by 1.22.7 times and 2.4x10(3) -1.1x10(4) times compared with STT-CIM and CRAM based on spintronic memory. Finally, the recognition accuracy can reach 98.65% and 91.11% on MNIST and CIFAR10, respectively.

关键词： computing in memory time-domain spintronics digit recognition convolutional neural networks

来源：评论

学校读者我要写书评

暂无评论

Nonvolatile Low-Cost Approximate Spintronic Full Adders for computing in memory Architectures

引用

IEEE TRANSACTIONS ON MAGNETICS 2020年第4期56卷 1-8页

作者： Rajaei, Ramin Amirany, Abdolah Univ Notre Dame Dept Comp Sci & Engn Notre Dame IN 46556 USA Shahid Beheshti Univ Dept Elect Engn Tehran *** Iran

In this article, four novel approximate full-adder (AXFA) circuits based on the emerging magnetic tunnel junction (MTJ) device is proposed. The proposed magnetic FAs (MFAs) offer full nonvolatility, low area, and considerably lower energy consumption than their previous counterparts. Also, two of the proposed MFAs have the advantage of single event upset (SEU) tolerance. Simulation results reveal that the proposed designs offer over 50% energy efficiency in comparison with the considered previous fully nonvolatile MFAs. Using the proposed adders in the design of an approximate Gaussian filter, we showed that the filtered noisy images have almost the same results as the accurate Gaussian filter. The proposed MFAs have an accurate carry-out output and an approximate sum output with an error distance of 2.

关键词： Approximate computing computing in memory magnetic tunnel junction (MTJ) spintronic

来源：评论

学校读者我要写书评

暂无评论

computing in memory Using Doubled STT-MRAM With the Application of Binarized Neural Networks

引用

IEEE MAGNETICS LETTERS 2023年 14卷 1页

作者： Nemati, Seyed Hassan Hadi Eslami, Nima Moaiyeri, Mohammad Hossein Shahid Beheshti Univ Fac Elect Engn Tehran *** Iran

The computing-in-memory (CiM) approach is a promising option for addressing the processor-memory data transfer bottleneck while performing data-intensive applications. In this letter, we present a novel CiM architecture based on spin-transfer torque magnetic random-access memory, which can work in computing and memory modes. In this letter, two spintronic devices are considered per cell to store the main data and its complement to address the reliability concerns during the read operation, which also provides a fascinating ability for performing reliable Boolean operations (all basic functions), binary/ternary content-addressable memory search operation, and multi-input majority function. Since the developed architecture can perform bitwise xnor operations in one cycle, a resistive-based accumulator has been designed to perform multi-input majority production to improve the structure for implementing fast and low-cost binary neural networks (BNNs). To this end, multiplication, accumulation, and passing through the activation function are accomplished in three cycles. The simulation result of exploiting the architecture in the BNN application indicates 86%-98% lower power-delay product than existing architectures.

关键词： Spin electronics computing in memory spin-transfer torque magnetic random-access memory binary/ternary content-addressable memory resistive-based majority function binary neural network

来源：评论

学校读者我要写书评

暂无评论

Intrinsic Capacitance based Multi bit computing in memory 18

Intrinsic Capacitance based Multi bit Computing in Memory

引用

18th International SoC Design Conference (ISOCC)

作者： Lee, Young Kyu Yeo, Minjune Cho, Seokhee Jung, Seong-Ook Yonsei Univ Sch Elect Engn Seoul South Korea

ISBN: (纸本)9781665401746

computing in memory (CIM) technique is being researched for process multiply-and-accumulate operation which is used in deep neural networks efficiently. Conventional CIM architecture only supports binary neural network which has lower accuracy. Some approaches use capacitor for multi bit operation. However, because capacitor has large size, the area efficiency of CIM macro is degraded. This paper proposes CIM macro structure that supports multi bit operation using parasitic capacitance of transistor. The proposed structure does not need additional capacitor and thus, it can achieve area efficient multi bit operation.

关键词： computing in memory Deep Neural Networks Multi bit computing SRAM

来源：评论

学校读者我要写书评

暂无评论

MLFlash-CIM: Embedded Multi-Level NOR-Flash Cell based computing in memory Architecture for Edge AI Devices 3

MLFlash-CIM: Embedded Multi-Level NOR-Flash Cell based Compu...

引用

IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS)

作者： Zeng, Sitao Zhang, Yuxin Zhu, Zhiguo Qin, Zhaolong Dou, Chunmeng Si, Xin Li, Qiang Univ Elect Sci & Technol China Chengdu Peoples R China Chinese Acad Sci Inst Microelect Beijing Peoples R China Southeast Univ Nanjing Peoples R China

ISBN: (纸本)9781665419130

computing-in-memory (CIM) is a promising method to overcome the well-known "Von Neumann Bottleneck" with computation insides memory, especially in edge artificial intelligence (AI) devices. In this paper, we proposed a 40nm 1Mb Multi-Level NOR-Flash cell based CIM (MLFlash-CIM) architecture with hardware and software co-design. Modeling of proposed MLFlash-CIM was analyzed with the consideration of cell variation, number of activated cells, integral non-linear (INL) and differential non-linear (DNL) of input driver, and quantization error of readout circuits. We also proposed a multi-bit neural network mapping method with 1/n top values and an adaptive quantization scheme to improve the inference accuracy. When applied to a modified VGG-16 Network with 16 layers, the proposed MLFlash-CIM can achieve 92.73% inference accuracy under CIFAR-10 dataset. This CIM structure also achieved a peak throughput of 3.277 TOPS and an energy efficiency of 35.6 TOPS/W for 4-bit multiplication and accumulation (MAC) operations.

关键词： Multi-Level NOR-Flash computing in memory Artificial Intelligence Convolutional Neural Network

来源：评论

学校读者我要写书评

暂无评论

Built-in Self-Test and Built-in Self-Repair Strategies Without Golden Signature for computing in memory

Built-in Self-Test and Built-in Self-Repair Strategies Witho...

引用

Design, Automation and Test in Europe Conference and Exhibition (DATE)

作者： Tsai, Yu-Chih Ting, Wen-Chien Wang, Chia-Chun Chang, Chia-Cheng Liu, Ren-Shuo Natl Tsing Hua Univ Hsinchu Taiwan

ISBN: (纸本)9798350396249

This paper proposes built-in self-test (BIST) and built-in self-repair (BISR) strategies for computing in memory (CIM), including a novel test method and two repair schemes. They all focus on mitigating the impacts of inherent and inevitable CIM inaccuracy on convolution neural networks (CNNs). Regarding the proposed BIST strategy, it exploits the distributive law to achieve at-speed CIM tests without storing testing vectors or golden results. Besides, it can assess the severity of the inherent inaccuracies among CIM bitlines instead of only offering a pass/fail outcome. In addition to BIST, we propose two BISR strategies. First, we propose to slightly offset the dynamic range of CIM outputs toward the negative side to create a margin for negative noises. By not cutting CIM outputs off at zero, negative noises are preserved to cancel out positive noises statistically, and accuracy impacts are mitigated. Second, we propose to remap the bitlines of CIM according to our BIST outcomes. Briefly speaking, we propose to map the least noisy bitlines to be the MSBs. This remapping can be done in the digital domain without touching the CIM internals. Experiments show that our proposed BIST and BISR strategies can restore CIM to less than 1% Top-1 accuracy loss with slight hardware overhead.

关键词： computing in memory built-in self-test built-in self-repair accelerator convolutional neural networks

来源：评论

学校读者我要写书评

暂无评论

Automatic Reference Current Architecture in computing in memory by MRAM

Automatic Reference Current Architecture in Computing in Mem...

引用

IEEE Eurasia Conference on IOT, Communication and Engineering (IEEE ECICE)

作者： Chen, Tsao-Lun Tseng, Wei-Tang Yuan Ze Univ 135 Far East Rd Taoyuan Taiwan

ISBN: (纸本)9781728125015

This paper uses STT-MRAM architecture to implement computing in memory (CIM). In traditional CIM architecture, sensing amplifier often uses a fixed current to be a reference current. It can't adapt different sensing margin with different turn on word-line and will make the sensing output error, when turning on too many word-line. We present an automatic reference current by using extra memory area to calculate the midden of high and low current. This reference current will change with sensing margin. Finally, we can sense high and low within the 16 word-lines.

关键词： STT MRAM computing in memory Sensing Amplifier

来源：评论

学校读者我要写书评

暂无评论

Dynamic computing in memory (DCIM) in Resistive Crossbar Arrays 36

Dynamic Computing in Memory (DCIM) in Resistive Crossbar Arr...

引用

36th IEEE International Conference on Computer Design (ICCD)

作者： Motaman, Seyedhamidreza Ghosh, Swaroop Penn State Univ Comp Sci & Engn University Pk PA 16802 USA

ISBN: (纸本)9781538684771

With Von-Neumann computing struggling to match the energy-efficiency of biological systems, there is pressing need to explore alternative computing models. Recent experimental studies have revealed that Resistive Random Access memory (RRAM) is promising alternative for DRAM. Resistive crossbar arrays possess many promising features that can not only enable high-density and low-power storage but also non Von-Neumann compute models. Most recent works focus on dot product operation with RRAM crossbar arrays, and therefore are not flexible to implement various logical functions. We propose a low-power dynamic computing in memory system which can implement various functions in Sum of Product (SOP) form in RRAM crossbar array architecture. We evaluate the proposed technique by performing simulation over wide range of MCNC benchmarks. Simulation results show 1.42X and 20X latency improvement as well as 2.6X and 12.6X power saving compared to static [9] and MAGIC [10] computing in memory methods.

关键词： Resistive RAM Sense Margin computing in memory Process Variation Crossbar Array

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：