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IEEE International Symposium on Circuits and Systems (IEEE ISCAS)

作者： Chen, Yuzong Lu, Lu Lu, Yuncheng Kim, Tony Tae-Hyoung Nanyang Technol Univ Sch Elect & Elect Engn Singapore Singapore

ISBN: (纸本)9781728192017

This paper presents a multi-functional resistive random access memory (ReRAM) macro using a novel 4T2R bit-cell. The proposed 4T2R ReRAM enables 2-dimensional (2-D) memory access, which offers significant latency and energy reductions for many applications such as matrix operations. Besides non-volatile storage, the proposed 4T2R ReRAM can support two types of computing in-memory operations: ternary content-addressable memory (TCAM) and logic in-memory (LIM). Evaluations on various matrix operations show that the proposed 4T2R ReRAM with 2-D access capability can reduce memory access latency and energy by up to 88% and 82%, respectively compared with conventional 1T1R ReRAM. For TCAM, the proposed 4T2R bit-cell takes a smaller area than SRAM-based TCAM cell, while achieves a comparable search speed. For LIM, we propose an optimized LIM full adder (LIM-FA) that improves the delay and the power by 3.2x and 1.6x, respectively compared with prior LIM-FAs.

关键词： resistive random access memory (ReRAM) TCAM computing in-memory 2-dimensional memory access

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Atomic Layer-Deposited HfAlOx-Based RRAM with Low Operating Voltage for computing in-memory Applications

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NANOSCALE RESEARCH LETTERS 2019年第1期14卷 51-51页

作者： He, Zhen-Yu Wang, Tian-Yu Chen, Lin Zhu, Hao Sun, Qing-Qing Ding, Shi-Jin Zhang, David Wei Fudan Univ Sch Microelect State Key Lab ASIC & Syst Shanghai 200433 Peoples R China

With Moore's law closing to its physical limit, traditional von Neumann architecture is facing a challenge. It is expected that the computing in-memory architecture-based resistive random access memory (RRAM) could be a potential candidate to overcome the von Neumann bottleneck problem of traditional computers [Backus, J, Can programming be liberated from the von Neumann style?, 1977]. In this work, HfAlOx-based RRAM which is compatible with CMOS technology was fabricated by an atomic layer deposition (ALD) process. Metal Ag and TaN are selected as top electrodes (TE). Experiments show that the Ag/HfAlOx/Pt device has demonstrated advantages as a memory-computing device because of the low set voltage (0.33 similar to 0.6V) which means low power consumption and good uniformity. Based on a Ag/HfAlOx/Pt structure, IMP logic was implemented at high speed by applying a 100-ns high-frequency low-voltage pulse (0.3V and 0.6V). After two steps of IMP implementation, NAND can also be obtained.

关键词： computing in-memory RRAM Switching Implemented

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A High Reliability Sense Amplifier for computing in-memory with STT-MRAM

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SPIN 2020年第2期10卷

作者： Zhang, Li Tang, Hualian Xu, Beilei Zhuang, Yiqi Bao, Junlin Xidian Univ Sch Microelect Xian 710071 Peoples R China

In the era of big data, massive data requires processing efficiently. However, the limited data bandwidth between the memory and the processor in conventional computer systems could not meet the requirement of data transferring. computing in-memory has been considered an effective solution to address this problem. In this paper, based on the spin transfer torque-magnetic random access memory (STT-MRAM), a computing in-memory architecture with as few peripheral circuits as possible is proposed. This computing in-memory architecture gives the specific reference cell so that two rows in one array can be activated simultaneously to perform bitwise logic operations, such as OR/NOR and AND/NAND. In addition, with technology scaling down, STT-MRAM suffers from high sensitivity to process variation, which results in more device mismatch in a sense circuit. Additionally, the negative bias temperature instability (NBTI) seriously affects the life of PMOS transistors used in a sense circuit. In this paper, a high-reliability sense amplifier for computing in-memory with STT-MRAM is proposed. By using two self-enabled switching transistors, the proposed sense amplifier not only can decrease the NBTI effect on PMOS transistors but also can achieve a low sensing error rate. Using a CMOS 40 nm design-kit and an accurate compact model of the STT magnetic tunnel junction (MTJ), mixed transient and statistical simulations have been present to demonstrate the functionality and performance of the proposed circuits.

关键词： computing in-memory STT-MRAM sense amplifier reliability

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CD-MAC: mixed-signal binary/ternary in-memory computing accelerator for power-constrained MAC processing

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JOURNAL OF SUPERcomputing 2025年第1期81卷 1-26页

作者： Dabbagh, Arsalan Karamimanesh, Mehrzad Hassanli, Kourosh Abiri, Ebrahim Shiraz Univ Technol Dept Elect & Elect Engn Modares Blvd Shiraz *** Fars Iran

The shortcomings of traditional von Neumann architectures have become more evident in the artificial intelligence (AI) and machine learning (ML) era. The continuous data flow between memory and processing units, combined with the demand for frequent and extensive processing, has led to decreased throughput and increased power consumption. Recent research explores the use of low-precision values like binary and ternary for AI hardware implementation algorithms as a potential solution. In this paper, a Charge-domain multiply-and-accumulate (CD-MAC) operation using a mixed-signal SRAM-based computing-in-memory accelerator is introduced, which performs binary/ternary processes to expedite ML and AI execution. These binary/ternary MAC operations are performed in situ through a combination of discharge-based and charge-sharing analog computing techniques. The proposed CD-MAC is simulated in 15-nm FinFET technology and demonstrates a 1.7x-5.8x improvement in TOPS/W compared to previous low-precision accelerators, consuming 1.63 W. It achieved an energy efficiency of 697 TOPS/W and a speed of 65 GOPS for ternary MAC operations, with 88% test accuracy in a recognition task involving random digit and letter images. The use of clustering techniques in the cell array enhances the accelerator's accuracy and compatibility for various MAC operations, leading to reduced power consumption during computation.

关键词： computing in-memory Binary/ternary MAC accelerator Low-precision AI AI hardware

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High-throughput in-memory bitwise computing based on a coupled dual-SRAM array with independent operands

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INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS 2024年第0期 2381-2397页

作者： Wu, Hongbiao Lin, Zhiting Wu, Xiulong Zhao, Qiang Lu, Wenjuan Peng, Chunyu Anhui Univ Sch Integrated Circuits Hefei 230601 Peoples R China

The successful implementation of artificial intelligence algorithms depends on the capacity to execute numerous repeated operations, which, in turn, requires systems with high data throughput. Although emerging computing-in-memory (CIM) eliminates the need for frequent data transfer between the memory and processing blocks and enables parallel activation of multiple rows, the traditional structure, where each row has only one identical input value, significantly limits its further application. To solve this problem, this study proposes a dual-SRAM CIM architecture in which two SRAM arrays are coupled such that all operands are different, thus rendering the use of CIM considerably more flexible. The proposed dual-SRAM array was implemented through a 55-nm process, essentially delivering a frequency of 361 MHz for a 1.2-V supply and energy efficiency of 161 TOPS/W at 0.9 V supply. This work proposes a mutually coupled SRAM CIM structure that, in addition to supporting existing CNN or BNN, can achieve pixel to pixel mode computation with independent operands as the main feature, such as ***

关键词： computing in-memory high-throughput independent operands SRAM

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Error-Aware Training for In-RRAM computing Design Considering Non-Ideal Effects in RRAM Crossbar Array and Peripheral Circuits

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ACM Journal on Emerging Technologies in computing Systems 2025年第2期21卷 1-22页

作者： Shih-Han Chang Ray-Hong Yen Chien-Nan Liu Institute of Electronics National Yang Ming Chiao Tung University Hsinchu Taiwan

In recent years, computing in-memory (CIM) technology has been proposed to solve the bottleneck of data movement in AI edge designs. In-RRAM computing (IRC) is a popular architecture due to its low leakage current and high density. However, to integrate some simple computation in memory, the IRC designs often adopt analog operations, which bring new issues to the computation accuracy. In order to speed up the verification of computation results, an accurate behavioral model for the RRAM crossbar array and the peripheral circuits with non-ideal effects is proposed. By using the proposed behavioral model, we build a hierarchical simulation framework for the IRC system to provide runtime errors for circuit design optimization and CNN training. As shown in the experimental results, the simulation accuracy of the IRC system is greatly improved by considering the contribution from peripheral circuits, but the simulation time can be reduced from several hours to 1 minute. The error-aware CNN training with the proposed models efficiently improves the CNN inference accuracy in real applications, which solves the accuracy and efficiency issues in traditional approaches.

关键词： Analog behavioral model computing in-memory RRAM crossbar array CNN training

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BSTCIM: A Balanced Symmetry Ternary Fully Digital In-MRAM computing Macro for Energy Efficiency Neural Network

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2024年第12期71卷 6114-6127页

作者： Tong, Zhongzhen Li, Chenghang Wang, Chao Zhao, Suteng Peng, Qianyong Yan, Zhenyu Zhang, Siqi Zhou, Daming Wang, Zhaohao Lin, Xiaoyang Zhao, Weisheng Beihang Univ Hangzhou Int Innovat Inst Natl Key Lab Spintron Hangzhou 311115 Peoples R China Beihang Univ Fert Beijing Inst Sch Integrated Circuit Sci & Engn MIIT Key Lab Spintron Beijing 100191 Peoples R China Beihang Univ Sch Integrated Circuit Sci & Engn Beijing 100191 Peoples R China

Silicon-based traditional binary computing in-memory (TBCIM) architectures are approaching their energy efficiency and throughput limits owing to challenges facing Moore's Law. Thus, it is essential to explore architecture based on novel devices and computing paradigms to fulfill data-centric applications, such as artificial intelligence. In this paper, we propose a balanced symmetry ternary (BST) fully digital in-MRAM computing macro (BSTCIM) using hybrid voltage-gated spin-orbit torque magnetic tunnel junctions (VGSOT-MTJ) and gate-all-around carbon nanotube field-effect-transistors (GAA-CNTFET) technology. The overall computing is based on the highest efficiency multi-bit ternary system. BSTCIM includes a ternary dot product (TDP) unit with 4 GAA-CNTFETs and 2 VGSOT-MTJs achieving TDP operation without complex logic circuits. The multi-bit ternary multiply-and-accumulate (MAC) operation is realized through the proposed ternary adder tree and ternary post adder which accumulate TDP results within the digital domain enabling high accuracy neural network inference. Furthermore, due to the advantages of BST, ternary signed MAC is more easily performed compared to TBCIM macros that adapt 2's complement or separate signed bit calculations. BSTCIM with 288 kb is simulated, achieving throughput and energy efficiency of 0.72 TOPS and 54.5 TOPS/W, respectively, at a 0.6 V supply voltage and 1.15 TOPS and 33.7 TOPS/W, respectively at a 0.8 V supply voltage with 8b-IN, 8b-W, and 20b-OUT. Moreover, the figure-of-merit for BSTCIM is 1.13-33.6 times higher than that of existing CIM macros.

关键词： computing in-memory balanced symmetry ternary ternary CIM MRAM GAA-CNTFET VGSOT-MTJ

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A High Throughput In-MRAM-computing Scheme Using Hybrid p-SOT-MTJ/GAA-CNTFET

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2024年第2期71卷 606-619页

作者： Tong, Zhongzhen Xu, Yilin Liu, Yunlong Duan, Xinrui Tang, Hao Zhao, Suteng Li, Chenghang Lin, Zhiting Wu, Xiulong Wang, Zhaohao Lin, Xiaoyang Beihang Univ Inst Int Innovat Natl Key Lab Spintron Hangzhou 311115 Peoples R China Beihang Univ Fert Beijing Inst Sch Integrated Circuit Sci & Engn MIIT Key Lab Spintron Beijing 100191 Peoples R China Beihang Univ Sch Integrated Circuit Sci & Engn Beijing 100191 Peoples R China Anhui Univ Sch Integrated Circuits Anhui Prov High Performance Integrated Circuit Eng Hefei 230601 Peoples R China

Silicon-based semiconductor transistors are approaching their physical limits due to shrinking feature sizes. Simultaneously, traditional silicon-based von Neumann architectures exhibit significant latency and power consumption issues in data-centric applications, such as the Internet of Things and artificial intelligence. To tackle these challenges, this study introduces a novel approach: Magnetoresistance Random Access memory (MRAM) computing in-memory (CIM) using gate-all-around carbon nanotube field-effect transistors (GAA-CNTFET). The proposed MRAM array comprised three transistors and one perpendicular magnetic anisotropy spin-orbit torque magnetic tunnel junction (p-SOT-MTJ) (3T1M) cell and achieves full-array Boolean logic operations and half/full-adder operations. The calculated results can be stored in-situ during the computing phase without requiring additional peripheral circuits. A 16 Kb MRAM was simulated in both GAA-CNTFET/p-SOT-MTJ and 14-nm FinFET/p-SOT-MTJ technologies to examine the effectiveness of the proposed design. Compared to its 14-nm FinFET/p-SOT-MTJ counterparts, the write and computing latencies of the GAA-CNTFET/p-SOT-MTJ CIM macro were reduced by approximately 21% and 20.6%, respectively, while the read and computing energy consumption by approximately 45.3% and 24.7%, respectively. Moreover, the proposed in-memory Boolean logic throughput was 8192 GOPS, which was approximately 160-250 times higher than that of existing CIM solutions, in which only two rows of word lines can be activated.

关键词： Boolean logic operation magnetoresistance random access memory computing in-memory in-situ storing half/full adder gate-all-around carbon nanotube field-effect-transistor von Neumann bottleneck

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Time Domain Analog Neuromorphic Engine Based on High-Density Non-Volatile memory in Single-Poly CMOS

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IEEE ACCESS 2022年 10卷 49154-49166页

作者： Rizzo, Tommaso Strangio, Sebastiano Iannaccone, Giuseppe Univ Pisa Dept Informat Engn I-56122 Pisa Italy Quantavis Srl I-56123 Pisa Italy

Increasing the energy efficiency of deep learning systems is critical for improving the cognitive capability of edge devices, often battery operated, as well as for data centers, constrained by the total power envelope. Specialized architectures accelerated by analog vector-matrix multipliers (VMMs) can reduce by orders of magnitude the energy per operation, since the reduced precision of analog computation does not undermine the classification accuracy of the neural network. We show an analog vector-matrix multiplier fabricated with industry-standard 0.18 mu m CMOS process, exploiting a single-transistor non-volatile analog memory cell and dedicated technology circuit co-design. The design is focused on implementation in neural networks performing offline training. The VMM performs the analog multiplication of a vector of inputs, encoded in the duration of time pulses, times a matrix of weights, encoded in the programmable currents of the memory cells. A 1.72 mu m(2) memory cell is realized with a single transistor with floating gate, which can be operated as a two-terminal analog memristive device with more than 64 programmable current levels and high I-high/I-low ratio (> 10(3)), tuned by the charge injected in the floating gate. A small-area charge amplifier is used to convert the multiply and accumulate operation result into a voltage. System-level projections based on our measurements and simulations provide a throughput of 333.17 GOps/s and an energy efficiency of 122.3 TOps/J, higher than comparable-precision VMMs reported in the literature, and an equivalent area per cell down to 2.15 mu m(2), lower than any similar state-of-the-art solution. Of critical importance in view of translation to industry, our proposal uses in a new way an industry-standard low-cost single-poly CMOS process flow.

关键词： Analog computing analog memory analog neural networks analog non-volatile memory computing in-memory neuromorphic computing

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Energy Efficient Memristive Transiently Chaotic Neural Network for Combinatorial Optimization

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2024年第8期71卷 3708-3716页

作者： Bao, Han Ren, Pengyu Xu, Kehong Yang, Ling Zhou, Houji Li, Jiancong Li, Yi Miao, Xiangshui Huazhong Univ Sci & Technol Sch Integrated Circuits Wuhan 430074 Peoples R China Univ Michigan Dept Elect Engn & Comp Sci Ann Arbor MI 48109 USA Hubei Yangtze Memory Labs Wuhan 430205 Peoples R China

The utilization of memristive analog-digital mixed in-memory computing has significantly tackled the issues of massive computing resources and time delays in solving combinatorial optimization problems. However, further improvements in computing energy efficiency are still desirable for resource-constrained conditions and practical applications. Therefore, in this work, a memristive analog transiently chaotic neural network (TCNN) system is proposed to solve the traveling salesman problems (TSPs), which is consisted of 1) a memristor array to perform matrix-vector multiplication for the network iteration;2) neuronal modules and nonlinear activation function modules to emulate the basic functions of the network;3) chaotic simulated annealing (CSA) modules to improve the solution performance at extremely low hardware overhead. Based on these, after mapping the TSPs onto the memristor array, the proposed TCNN can self-iterate to convergence states to solve the problems with high performance. Compared to prior analog-digital mixed ones, the analog system can eliminate the extra control and data conversions during the network solving process, and achieve an 8 x reduction in the total energy consumption in consecutive solving tasks.

关键词： Memristors Analog-digital conversion Hardware Neurons Circuits Urban areas Simulated annealing computing in-memory memristor analog computing combinatorial optimization problems transiently chaotic neural network

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