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An ultra-low power SNN co-processor based on differential-pair SRAM and memristive memory with reconfigurable computing-in-memory array and coding scheme

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JAPANESE JOURNAL OF APPLIED PHYSICS 2025年第4期64卷

作者： Guo, Yaolei Deng, Liangyao Liu, Jinxu Tang, Chenhao Cheng, Yue Chen, Wenrui Ouyang, Ping Zhang, Yishu Cheng, Yongpeng Ma, Yitao Zhejiang Univ Coll Intergrated Circuits Hangzhou Peoples R China Zhejiang ICsprout Semicond Co Ltd Ltd Hangzhou Peoples R China ZJU Hangzhou Global Sci & Technol Innovat Ctr Hangzhou Peoples R China

This paper presents an ultra-low-power spiking neural network co-processor (RSNNP) with a reconfigurable computing-in-memory (CiM) cell array, leveraging both differential-pair SRAM and memristive memory. The proposed RSNNP introduces adaptability through three reconfigurable strategies: supporting both volatile (SRAM) and non-volatile (memristive) memory cell, free-extending the CiM array scale, and flexible-switching between rate and temporal coding schemes. A prototype chip, fabricated using 55 nm technology, achieves exceptional efficiency, with power consumption as low as 0.057 mu W (@SRAM) and 0.0102 mu W (@memristive) for a 24 fps image recognition task. Experimental results demonstrate the RSNNP's superiority in adapting to different SNN tasks and outperforming state-of-the-art SNN processors in power efficiency with lower power consumption. This work marks a significant step toward energy-efficient and adaptable SNN computation, suitable for edge computing and neuromorphic hardware applications.

关键词： neuromorphic processor computing-in-memory memristive utral-low-power

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A 0.000159 mm2 2.9 μm-pitch 4.3fJ/Conv 6-bit SAR ADC for high throughput parallel readout of analog SRAM computing-in-memory

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MICROELECTRONICS JOURNAL 2025年 160卷

作者： Wu, Lin Feng, Lichen Liu, Yunlong Qian, Libo Xia, Yinshui Zhu, Zhangming Xidian Univ Sch Integrated Circuits Key Lab Analog Integrated Circuits & Syst Minist Educ Xian 710071 Peoples R China Ningbo Univ Sch Elect Engn & Comp Sci Ningbo 315211 Peoples R China

Numerous SRAM-based analog computing-in-memory (CIM) macros have been verified in silicon to show great energy efficiency improvement. However, the large area of the existing analog-digital-converters (ADCs), especially the wide pitches between the ADCs, limit the number of computing results that can be quantized and readout in parallel. In this paper, we propose a 2.9 mu m-pitch 4.3fJ/conv 6-bit SAR ADC in 28 nm CMOS process. The area and power consumption of the complete ADC are significantly decreased by improving the finger-type differential capacitor in the unit-length DAC technology, and using the improved clock generation circuit and fully dynamic latch in the Vcm-based switching scheme. The proposed ADC occupies only 0.000159 mm2 with the pitch of 2.9 mu m, which can be aligned with as few bitcell columns as possible, showcasing superior potential for improving both throughput and energy efficiency of analog CIM macros.

关键词： computing-in-memory SAR ADC Unit-length DAC Pitch

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ArPCIM: An Arbitrary-Precision Analog computing-in-memory Accelerator With Unified INT/FP Arithmetic

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2025年第5期72卷 2229-2242页

作者： Zhou, Zhiwei Li, Jiancong Jia, Han Yang, Ling Zhou, Houji Bao, Han Fu, Yuyang Li, Yi Miao, Xiangshui Huazhong Univ Sci & Technol Sch Integrated Circuits Hubei Key Lab Adv Memories Wuhan 430074 Peoples R China Hubei Yangtze Memory Labs Wuhan 430205 Peoples R China

Analog computing-in-memory (ACIM) breaks the von Neumann bottleneck and significantly improves energy efficiency by enabling parallel matrix-vector-multiplication (MVM) operations. However, most existing ACIM accelerators are highly customized for specific precision formats, lacking the generality to support efficiently arbitrary precision in both integer (INT) and floating-point (FP) formats. In this work, we present an arbitrary precision analog computing-in-memory (ArPCIM) accelerator with unified INT/FP arithmetic to address this limitation. We introduce a CIM-friendly INT/FP arithmetic to convert FP numbers into INT numbers for efficient execution on CIM, minimizing precision loss through local pre-alignment and dynamic bit-weight slicing methods. In addition, we implement multi-level reconfigurable precision circuits, featuring both intra-and inter-processing element (PE) reconfigurability, which supports precision ranging from 1-bit to 47-bit. Experimental results show that our ArPCIM accelerator achieves up to 4.09 x and 5.37 x improvement in energy efficiency and area efficiency, respectively, compared with state-of-the-art arbitrary precision digital CIM. Our ArPCIM accelerator offers the flexibility to meet diverse computational needs while maintaining high energy efficiency and accuracy, paving the way for versatile CIM acceleration across various fields.

关键词： Arbitrary precision computing-in-memory floating-point reconfigurable architecture

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8T-SRAM computing-in-memory Macro with Bitline Leakage Compensation

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CIRCUITS SYSTEMS AND SIGNAL PROCESSING 2025年 1-19页

作者： Peng, Chunyu Chen, Junbo Zhao, Mengyi Lu, Wenjuan Lin, Zhiting Hao, Licai Li, Xin Dai, Chenghu Wu, Xiulong Anhui Univ Sch Integrated Circuits Hefei 230601 Peoples R China Anhui Prov High Performance Integrated Circuit Eng Hefei 230601 Peoples R China

computing-in-memory (CIM) technology has been developed to improve computer hardware efficiency for intelligent big data applications. An 8T-SRAM CIM macro with bitline leakage compensation ability is proposed in this study. In SRAM read mode, the proposed circuit solves the problem of read failure caused by bitline leakage current. In the write operation, the proposed circuit writes through the double-wordline, which can effectively improve the write static noise margin (WSNM) of the bitcell and reduce its write delay. When performing XNOR-and-accumulation (XAC) operations, the proposed circuit can effectively compensate the offset of the accumulated results due to bitline leakage current, thereby reducing output errors. In addition, this circuit can also be configured as binary content-addressable memory (BCAM) mode, and leakage compensation can be performed in this mode. A logic-AND sense amplifier (LASA) structure is also proposed, which can be applied in the SRAM read and BCAM modes. The proposed circuit is simulated in 55 nm CMOS process, under 1.2 V supply voltage. The proposed system demonstrates an energy efficiency of 62.7 TOPS/W, and effectively improves the anti-leakage ability of the array in all three modes.

关键词： computing-in-memory Bitline leakage compensation XNOR and accumulation BCAM SRAM

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A 22-nm Delta-Sigma computing-in-memory SRAM Macro With Near-Zero-Mean Outputs and LSB-First ADCs for Edge AI Processing

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2025年

作者： Chen, Peiyu Zhao, Wentao Wu, Meng Shen, Linxiao Jia, Tianyu Huang, Ru Ye, Le Ma, Yufei Peking Univ Sch Integrated Circuits Beijing 100871 Peoples R China Peking Univ Adv Inst Informat Technol Hangzhou 311215 Peoples R China Peking Univ Inst Artificial Intelligence Beijing 100871 Peoples R China Peking Univ Sch Integrated Circuits Beijing 100871 Peoples R China

This work proposes a static random access memory (SRAM)-based delta-sigma computing-in-memory (Delta Sigma CIM) processor for edge intelligence applications in 22-nm CMOS technology. This Delta Sigma CIM processor effectively mitigates redundant operations associated with unchanged input features and adaptively adjusts computing-in-memory (CIM) outputs to achieve a near-zero-mean (NZM) distribution, thereby benefiting the energy-intensive analog-to-digital converters (ADCs). The proposed Delta Sigma CIM macro involves three main innovations at the architecture and circuit levels: first, it replaces absolute inputs with deltas computed from consecutive input values, resulting in a notable 35.8% reduction in energy consumption for the CIM array;second, the delta matrix-vector multiplications (MVMs) implemented by Delta Sigma CIM array can self-adaptively shift the analog CIM outputs to be NZM distributed, facilitating streamlined centralized data processing;and third, the introduction of a least significant bit first (LSB-first) ADC, whose number of conversions adjust dynamically based on instantaneous input values, allows for efficient analog output conversion of highly concentrated NZM analog data without compromising full-scale range or precision. Compared with state-of-the-art (SOTA) analog SRAM-based CIM macros, this work achieves superior area-energy efficiency product by 1.25x with up to 21.38 TOPS/W and 1.44 TOPS/mm(2) at full precision of 8b input, 8b weight, and 24b output, through bit-serial inputs and shifter-and-adder.

关键词： In-memory computing Energy efficiency Common Information Model (computing) Energy consumption Arrays Neural networks Computational efficiency Computer architecture Random access memory Hardware Analog computing computing-in-memory edge computing neural network accelerator static random access memory (SRAM)

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An 8-bit 160-MS/s Charge Injection SAR ADC With Build-In Offset Calibration for computing-in-memory Macros

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IEEE Transactions on Circuits and Systems II: Express Briefs 2025年

作者： Dong, Siwan Wang, Jingyu Xi’an University of Posts and Telecommunications School of Electronics Engineering Shaanxi Xi’an China Accusense Microelectronics Co. Ltd. Jiangsu Suzhou China

This paper presents an 8-bit column pitch-matched charge injection (CI) SAR ADC specifically designed for computing-in-memory (CIM) macros. We propose an area-efficient built-in calibration loop that reuses the DAC array to mitigate offset effects and enhance inference accuracy, significantly reducing the digital logic and trimming circuit area overhead compared to conventional background/foreground calibration methods. To preserve offset and quantization results, we implement dedicated digital logic featuring an optimized data buffer chain with local positive feedback for node voltage stabilization. Fabricated in 65nm CMOS technology, the ADC occupies 0.0013mm² while demonstrating significant performance improvements: offset reduction from 15.9mV (4 LSB) to 1.98mV (0.5 LSB), with measured DNL and INL within +0.5/-0.7 LSB and ±1 LSB respectively. Operating at 160 MS/s sampling rate, it achieves 44.9dB SNDR and 49.9dB SFDR for near-Nyquist full-scale inputs, while consuming 0.65 mW, resulting in a figure of merit (FoM) of 28.2 fJ/conversion step. © 2004-2012 IEEE.

关键词： computing-in-memory offset calibration SARADC

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computing-in-memory Architecture Using Energy-Efficient Multilevel Voltage-Controlled Spin-Orbit Torque Device

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IEEE TRANSACTIONS ON ELECTRON DEVICES 2020年第5期67卷 1972-1979页

作者： Shreya, Sonal Jain, Alkesh Kaushik, Brajesh Kumar Indian Inst Technol Roorkee Elect & Commun Engn Dept Roorkee 247667 Uttar Pradesh India

Conventional von Neumann architecture suffers from data trafficking and power hungriness between memory and processing units. Recent architectures escalating to overcome these limitations are near-memory architecture (NMA) and computing-in-memory (CiM) architecture (CMA). Spintronics-based devices, such as spin-transfer torque magnetic memory (STTM), spin-orbit torque magnetic memory (SOTM), differential spin Hall-effect-based magnetic memory (DSHEM), and multilevel voltage-controlled-SOT-based magnetic memory (MV-SOTM) are a few promising contenders for post-CMOS technology. MV-SOTM spin device is used in this study to showcase the CMA to perform basic logic operations namely AND/NAND, OR/NOR, and XOR/XNOR within the memory array. Furthermore, magnetic full adder (MFA) is implemented using CMA in MV-SOTM array. The performance of CMA design for MV-SOTM-based MFA is compared with SOTM-based MFA. The proposed CiM design for MV-SOTM-based MFA shows 29.2% and 12.22% performance improvement in terms of write energy and logic power, respectively. Moreover, up to 34% area reduction is achieved in comparison to SOTM-based CiM MFA.

关键词： computing-in-memory magnetic memory multilevel voltage-controlled spin-orbit torque magnetic memory (SOTM) spin-orbit torque

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Design memristor-based computing-in-memory for AI accelerators considering the interplay between devices, circuits, and system

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Science China(Information Sciences) 2023年第8期66卷 243-253页

作者： Junjie AN Linfang WANG Wang YE Weizeng LI Hanghang GAO Zhi LI Zhidao ZHOU Jinghui TIAN Jianfeng GAO Chunmeng DOU Qi LIU School of Microelectronics University of Science and Technology of China State key Lab of Fabrication Technologies for Integrated Circuits Institute of MicroelectronicsChinese Academy of Sciences School of Microelectronics University of Chinese Academy of Sciences Frontier Institute of Chip and System State Key Laboratory of ASIC and System Fudan University

Recent advances in developing beyond von Neumann architectures have moved the memristive devices to the forefront as one of the key enablers to realizing memristive computing-in-memory(m CIM)structures, which shows a great promise to boost the energy-efficiency and the performance of artificial intelligence(AI) chips. In this study, by considering the interactions between devices, circuits, and systems in the m CIM design, we propose several cross-layer design techniques, including(1) the BL-SL interactive forming protection(BSIFP) circuit that can reduce the voltage drop on the selected transistor, suppress the current overshoot by 65.96%, and improve the bit-cell density by more than 10.19%,(2) the clamping transistor trimming scheme(CTTS) to prevent the multiply-and-accumulate(MAC) signal margin degradation from chip-to-chip resistance variations, and(3) dynamic input-parallelism and output-precision(DIPOP) that can reduce the energy cost by 22.92% in a typical inference task with negligible accuracy loss. The results demonstrate the significant role of the cross-layer-interactive approach and provide a preliminary guideline for highly-efficient m CIM design.

关键词： memristor resistive memory computing-in-memory artificial intelligence cross-layer co-design

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CMN: a co-designed neural architecture search for efficient computing-in-memory-based mixture-of-experts

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Science China(Information Sciences) 2024年第10期67卷 100-114页

作者： Shihao HAN Sishuo LIU Shucheng DU Mingzi LI Zijian YE Xiaoxin XU Yi LI Zhongrui WANG Dashan SHANG Department of Electrical and Electronic Engineering The University of Hong Kong ACCESS-AI Chip Center for Emerging Smart Systems InnoHK Centers Key Lab of Fabrication Technologies for Integrated Circuits Chinese Academy of Sciences Laboratory of Microelectronics Devices and Integrated Technology Institute of MicroelectronicsChinese Academy of Sciences University of Chinese Academy of Sciences School of Microelectronics Southern University of Science and Technology

Artificial intelligence(AI) has experienced substantial advancements recently, notably with the advent of large-scale language models(LLMs) employing mixture-of-experts(MoE) techniques, exhibiting human-like cognitive skills. As a promising hardware solution for edge MoE implementations, the computing-in-memory(CIM) architecture collocates memory and computing within a single device, significantly reducing the data movement and the associated energy consumption. However, due to diverse edge application scenarios and constraints, determining the optimal network structures for MoE, such as the expert's location,quantity, and dimension on CIM systems remains elusive. To this end, we introduce a software-hardware co-designed neural architecture search(NAS) framework, CIM-based MoE NAS(CMN), focusing on identifying a high-performing MoE structure under specific hardware constraints. The results of the NYUD-v2 dataset segmentation on the RRAM(SRAM) CIM system reveal that CMN can discover optimized MoE configurations under energy, latency, and performance constraints, achieving 29.67×(43.10×) energy savings,175.44×(109.89×) speedup, and 12.24× smaller model size compared to the baseline MoE-enabled Visual Transformer, respectively. This co-design opens up an avenue toward high-performance MoE deployments in edge CIM systems.

关键词： mixture-of-experts computing-in-memory neural architecture search resistive random-access memory static random-access memory

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A Robust 8-Bit Non-Volatile computing-in-memory Core for Low-Power Parallel MAC Operations

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2020年第6期67卷 1867-1880页

作者： Zhang, Sai Huang, Kejie Shen, Haibin Zhejiang Univ Coll Informat Sci & Elect Engn Hangzhou 310058 Peoples R China

The Artificial Intelligence (AI) in edge computing is requesting new processing units with a much higher computing-power ratio. The emerging resistive Non-Volatile memory (NVM) with the in-memory computing capability may greatly advance the AI hardware technologies. In this paper, we propose the use of binary resistive memory to form an 8-bit fixed-point data/weight for AI computing. A robust computing-in-memory (CIM) core with digital input and analog output Multiplication-and-Accumulation (MAC) circuit is proposed. The corresponding integration scheme and Successive Approximation Register Analog-to-Digital Converter (SAR ADC) based data conversion scheme are also presented. The simulation results show that the proposed CIM core achieves 7.26 bit of Effective Number of Bits (ENOB) with 0.78mW (256*1) power consumption and 1.85M/s computing speed. Compared with previously reported CIM implementations and Deep Learning Accelerators (DLAs) (without CIM ability), our design achieves 2.23-7.26x better energy efficiency in 8-bit input 8-bit weight pattern, and achieves relatively high accuracy with LeNet and AlexNet.

关键词： Nonvolatile memory Artificial intelligence Random access memory Common Information Model (computing) Robustness Computer architecture Common Information Model (electricity) Non-volatile memory multiplication-and-accumulation computing-in-memory resistive random access memory (RRAM) integral multiplier capacitors-shared SAR ADC

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