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An ultra-low power SNN co-processor based on differential-pair SRAM and memristive memory with reconfigurable computing-in-memory array and coding scheme

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JAPANESE JOURNAL OF APPLIED PHYSICS 2025年第4期64卷 04SP53-04SP53页

作者： Guo, Yaolei Deng, Liangyao Liu, Jinxu Tang, Chenhao Cheng, Yue Chen, Wenrui Ouyang, Ping Zhang, Yishu Cheng, Yongpeng Ma, Yitao Zhejiang Univ Coll Intergrated Circuits Hangzhou Peoples R China Zhejiang ICsprout Semicond Co Ltd Ltd Hangzhou Peoples R China ZJU Hangzhou Global Sci & Technol Innovat Ctr Hangzhou Peoples R China

This paper presents an ultra-low-power spiking neural network co-processor (RSNNP) with a reconfigurable computing-in-memory (CiM) cell array, leveraging both differential-pair SRAM and memristive memory. The proposed RSNNP introduces adaptability through three reconfigurable strategies: supporting both volatile (SRAM) and non-volatile (memristive) memory cell, free-extending the CiM array scale, and flexible-switching between rate and temporal coding schemes. A prototype chip, fabricated using 55 nm technology, achieves exceptional efficiency, with power consumption as low as 0.057 mu W (@SRAM) and 0.0102 mu W (@memristive) for a 24 fps image recognition task. Experimental results demonstrate the RSNNP's superiority in adapting to different SNN tasks and outperforming state-of-the-art SNN processors in power efficiency with lower power consumption. This work marks a significant step toward energy-efficient and adaptable SNN computation, suitable for edge computing and neuromorphic hardware applications.

关键词： neuromorphic processor computing-in-memory memristive utral-low-power

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A 22-nm Delta-Sigma computing-in-memory SRAM Macro With Near-Zero-Mean Outputs and LSB-First ADCs for Edge AI Processing

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2025年

作者： Chen, Peiyu Zhao, Wentao Wu, Meng Shen, Linxiao Jia, Tianyu Huang, Ru Ye, Le Ma, Yufei Peking Univ Sch Integrated Circuits Beijing 100871 Peoples R China Peking Univ Adv Inst Informat Technol Hangzhou 311215 Peoples R China Peking Univ Inst Artificial Intelligence Beijing 100871 Peoples R China Peking Univ Sch Integrated Circuits Beijing 100871 Peoples R China

This work proposes a static random access memory (SRAM)-based delta-sigma computing-in-memory (Delta Sigma CIM) processor for edge intelligence applications in 22-nm CMOS technology. This Delta Sigma CIM processor effectively mitigates redundant operations associated with unchanged input features and adaptively adjusts computing-in-memory (CIM) outputs to achieve a near-zero-mean (NZM) distribution, thereby benefiting the energy-intensive analog-to-digital converters (ADCs). The proposed Delta Sigma CIM macro involves three main innovations at the architecture and circuit levels: first, it replaces absolute inputs with deltas computed from consecutive input values, resulting in a notable 35.8% reduction in energy consumption for the CIM array;second, the delta matrix-vector multiplications (MVMs) implemented by Delta Sigma CIM array can self-adaptively shift the analog CIM outputs to be NZM distributed, facilitating streamlined centralized data processing;and third, the introduction of a least significant bit first (LSB-first) ADC, whose number of conversions adjust dynamically based on instantaneous input values, allows for efficient analog output conversion of highly concentrated NZM analog data without compromising full-scale range or precision. Compared with state-of-the-art (SOTA) analog SRAM-based CIM macros, this work achieves superior area-energy efficiency product by 1.25x with up to 21.38 TOPS/W and 1.44 TOPS/mm(2) at full precision of 8b input, 8b weight, and 24b output, through bit-serial inputs and shifter-and-adder.

关键词： In-memory computing Energy efficiency Common Information Model (computing) Energy consumption Arrays Neural networks Computational efficiency Computer architecture Random access memory Hardware Analog computing computing-in-memory edge computing neural network accelerator static random access memory (SRAM)

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A 0.000159 mm2 2.9 μm-pitch 4.3fJ/Conv 6-bit SAR ADC for high throughput parallel readout of analog SRAM computing-in-memory

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MICROELECTRONICS JOURNAL 2025年 160卷

作者： Wu, Lin Feng, Lichen Liu, Yunlong Qian, Libo Xia, Yinshui Zhu, Zhangming Xidian Univ Sch Integrated Circuits Key Lab Analog Integrated Circuits & Syst Minist Educ Xian 710071 Peoples R China Ningbo Univ Sch Elect Engn & Comp Sci Ningbo 315211 Peoples R China

Numerous SRAM-based analog computing-in-memory (CIM) macros have been verified in silicon to show great energy efficiency improvement. However, the large area of the existing analog-digital-converters (ADCs), especially the wide pitches between the ADCs, limit the number of computing results that can be quantized and readout in parallel. In this paper, we propose a 2.9 mu m-pitch 4.3fJ/conv 6-bit SAR ADC in 28 nm CMOS process. The area and power consumption of the complete ADC are significantly decreased by improving the finger-type differential capacitor in the unit-length DAC technology, and using the improved clock generation circuit and fully dynamic latch in the Vcm-based switching scheme. The proposed ADC occupies only 0.000159 mm2 with the pitch of 2.9 mu m, which can be aligned with as few bitcell columns as possible, showcasing superior potential for improving both throughput and energy efficiency of analog CIM macros.

关键词： computing-in-memory SAR ADC Unit-length DAC Pitch

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CMN: a co-designed neural architecture search for efficient computing-in-memory-based mixture-of-experts

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Science China(Information Sciences) 2024年第10期67卷 100-114页

作者： Shihao HAN Sishuo LIU Shucheng DU Mingzi LI Zijian YE Xiaoxin XU Yi LI Zhongrui WANG Dashan SHANG Department of Electrical and Electronic Engineering The University of Hong Kong ACCESS-AI Chip Center for Emerging Smart Systems InnoHK Centers Key Lab of Fabrication Technologies for Integrated Circuits Chinese Academy of Sciences Laboratory of Microelectronics Devices and Integrated Technology Institute of MicroelectronicsChinese Academy of Sciences University of Chinese Academy of Sciences School of Microelectronics Southern University of Science and Technology

Artificial intelligence(AI) has experienced substantial advancements recently, notably with the advent of large-scale language models(LLMs) employing mixture-of-experts(MoE) techniques, exhibiting human-like cognitive skills. As a promising hardware solution for edge MoE implementations, the computing-in-memory(CIM) architecture collocates memory and computing within a single device, significantly reducing the data movement and the associated energy consumption. However, due to diverse edge application scenarios and constraints, determining the optimal network structures for MoE, such as the expert's location,quantity, and dimension on CIM systems remains elusive. To this end, we introduce a software-hardware co-designed neural architecture search(NAS) framework, CIM-based MoE NAS(CMN), focusing on identifying a high-performing MoE structure under specific hardware constraints. The results of the NYUD-v2 dataset segmentation on the RRAM(SRAM) CIM system reveal that CMN can discover optimized MoE configurations under energy, latency, and performance constraints, achieving 29.67×(43.10×) energy savings,175.44×(109.89×) speedup, and 12.24× smaller model size compared to the baseline MoE-enabled Visual Transformer, respectively. This co-design opens up an avenue toward high-performance MoE deployments in edge CIM systems.

关键词： mixture-of-experts computing-in-memory neural architecture search resistive random-access memory static random-access memory

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ArPCIM: An Arbitrary-Precision Analog computing-in-memory Accelerator With Unified INT/FP Arithmetic

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2025年第5期72卷 2229-2242页

作者： Zhou, Zhiwei Li, Jiancong Jia, Han Yang, Ling Zhou, Houji Bao, Han Fu, Yuyang Li, Yi Miao, Xiangshui Huazhong Univ Sci & Technol Sch Integrated Circuits Hubei Key Lab Adv Memories Wuhan 430074 Peoples R China Hubei Yangtze Memory Labs Wuhan 430205 Peoples R China

Analog computing-in-memory (ACIM) breaks the von Neumann bottleneck and significantly improves energy efficiency by enabling parallel matrix-vector-multiplication (MVM) operations. However, most existing ACIM accelerators are highly customized for specific precision formats, lacking the generality to support efficiently arbitrary precision in both integer (INT) and floating-point (FP) formats. In this work, we present an arbitrary precision analog computing-in-memory (ArPCIM) accelerator with unified INT/FP arithmetic to address this limitation. We introduce a CIM-friendly INT/FP arithmetic to convert FP numbers into INT numbers for efficient execution on CIM, minimizing precision loss through local pre-alignment and dynamic bit-weight slicing methods. In addition, we implement multi-level reconfigurable precision circuits, featuring both intra-and inter-processing element (PE) reconfigurability, which supports precision ranging from 1-bit to 47-bit. Experimental results show that our ArPCIM accelerator achieves up to 4.09 x and 5.37 x improvement in energy efficiency and area efficiency, respectively, compared with state-of-the-art arbitrary precision digital CIM. Our ArPCIM accelerator offers the flexibility to meet diverse computational needs while maintaining high energy efficiency and accuracy, paving the way for versatile CIM acceleration across various fields.

关键词： Arbitrary precision computing-in-memory floating-point reconfigurable architecture

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RDCIM: RISC-V Supported Full-Digital computing-in-memory Processor With High Energy Efficiency and Low Area Overhead

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2024年第4期71卷 1719-1732页

作者： Yi, Wente Mo, Kefan Wang, Wenjia Zhou, Yitong Zeng, Yejun Yuan, Zihan Cheng, Bojun Pan, Biao Beihang Univ Sch Integrated Circuit Sci & Engn Beijing 100191 Peoples R China Hong Kong Univ Sci & Technol Guangzhou Microelect Thrust Funct Hub Guangzhou 510000 Peoples R China

Digital computing-in-memory (DCIM) that merges computing logic into memory has been proven to be an efficient architecture for accelerating multiply-and-accumulates (MACs). However, low energy efficiency and high area overhead pose a primary restriction for integrating DCIM in re-configurable processors required for multi-functional workloads. To alleviate this dilemma, a novel RISC-V supported full-digital computing-in-memory processor (RDCIM) is designed and fabricated with 55nm CMOS technology. In RDCIM, an adding-on-memory-boundary (AOMB) scheme is adopted to improve the energy efficiency of DCIM. Meanwhile, a multi-precision adaptive accumulator (MPAA) and a serial-parallel conversion supported SRAM buffer (SPBUF) are employed to reduce the area overhead caused by the peripheral circuits and the intermediate buffer for multi-precision support. The results show that the energy efficiency in our design is 16.6 TOPS/W (8-bit) and 66.3 TOPS/W (4-bit). Compared to related works, the proposed RDCIM macro shows a maximum energy efficiency improvement of 1.22x in a continuous computing scenario, an area saving of 1.22x in the accumulator, and an area saving of 3.12x in the input buffer. Moreover, in RDCIM, 5 fine-grained RISC-V extended instructions are designed to dynamically adjust the state of DCIM, reaching 1.2x computation efficiency.

关键词： computing-in-memory RISC-V extended instructions re-configurable precision

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A computing-in-memory-Based One-Class Hyperdimensional computing Model for Outlier Detection

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IEEE TRANSACTIONS ON COMPUTERS 2024年第6期73卷 1559-1574页

作者： Wang, Ruixuan Moon, Sabrina Hassan Hu, Xiaobo Sharon Jiao, Xun Reis, Dayane Villanova Univ Dept Elect & Comp Engn Villanova PA 19085 USA Univ S Florida Dept Comp Sci & Engn Tampa FL 33620 USA Univ Notre Dame Dept Comp Sci & Engn Notre Dame IN 46556 USA

In this work, we present ODHD, an algorithm for outlier detection based on hyperdimensional computing (HDC), a non-classical learning paradigm. Along with the HDC-based algorithm, we propose IM-ODHD, a computing-in-memory (CiM) implementation based on hardware/software (HW/SW) codesign for improved latency and energy efficiency. The training and testing phases of ODHD may be performed with conventional CPU/GPU hardware or our IM-ODHD, SRAM-based CiM architecture using the proposed HW/SW codesign techniques. We evaluate the performance of ODHD on six datasets from different application domains using three metrics, namely accuracy, F1 score, and ROC-AUC, and compare it with multiple baseline methods such as OCSVM, isolation forest, and autoencoder. The experimental results indicate that ODHD outperforms all the baseline methods in terms of these three metrics on every dataset for both CPU/GPU and CiM implementations. Furthermore, we perform an extensive design space exploration to demonstrate the tradeoff between delay, energy efficiency, and performance of ODHD. We demonstrate that the HW/SW codesign implementation of the outlier detection on IM-ODHD is able to outperform the GPU-based implementation of ODHD by at least 331.5x889 x in terms of training/testing latency (and on average 14.0x36.9x in terms of training/testing energy consumption).

关键词： Anomaly detection Task analysis Training Testing Software algorithms Forestry Computers Hyperdimensional computing outlier detection computing-in-memory hardware/software codesign

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A 16.38TOPS and 4.55POPS/W SRAM computing-in-memory Macro for Signed Operands Computation and Batch Normalization Implementation

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2024年第4期71卷 1706-1718页

作者： Qiao, Xin Guo, Qingyu Tang, Xiyuan Song, Jiahao Wei, Renjie Li, Meng Wang, Runsheng Wang, Yuan Peking Univ MPW Ctr Sch Integrated Circuits Key Lab Microelect Devices & Circuits MoE Beijing 100871 Peoples R China Beijing Adv Innovat Ctr Integrated Circuits Beijing 100871 Peoples R China

Edge artificial intelligence applications impose rigorous demands on local hardware to improve throughput and energy efficiency. computing-in-memory (CIM) architectures provide high parallel and energy-efficient solutions to accelerate the multiply-and-accumulate (MAC) operations in neural networks (NNs). While SRAM-based charge-domain CIM is achieving thousands of TOPS/W energy efficiency, it encounters limitations when dealing with full NN model deployments where both activations and weights are signed. This paper proposes an SRAM-based signed batch normalization (BN) CIM macro for supporting efficient bitwise sparse MAC computation with signed operands and BN operations in deep neural networks. The key features of this macro encompass: 1) a multibit weight unit for the optimization of bitstream sparsity and the sign bit computation, 2) a 2b-serial input configuration to increase throughput and the ADC energy amortization, and 3) a quantization-hardware co-design for the BN implementation. Measurement results show that the proposed 28 nm 64 Kb CIM macro achieves 16.38 TOPS throughput and 4.55 POPS/W energy efficiency, both normalized to 1b operands. The test accuracy of CIFAR10 is 92%, based on the ResNet18 model with co-design BN implementation at signed-8b precision activations and weights.

关键词： Common Information Model (computing) Energy efficiency Computational modeling Computational efficiency Voltage Quantization (signal) Capacitors computing-in-memory SRAM neural network signed operation batch normalization

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An Overview of computing-in-memory Circuits With DRAM and NVM

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2024年第3期71卷 1626-1631页

作者： Kim, Sangjin Yoo, Hoi-Jun Korea Adv Inst Sci & Technol Sch Elect Engn Daejeon 34141 South Korea

computing-in-memory (CIM) has emerged as an energy-efficient hardware solution for machine learning and AI. While static random access memory (SRAM)-based CIM has been prevalent, growing attention is directed towards leveraging dynamic random access memory (DRAM) and non-volatile memory (NVM) with its unique characteristics such as high-density and non-volatility. This brief reviews the evolving trends in DRAM and NVM-based CIM, which have faced unique challenges that arise from SRAM despite their advantages. For instance, the DRAM cell's density comes with leakage and refresh issues, impacting efficiency and computing accuracy. NVM-CIM faces computing accuracy challenges of resistance-based computation with low signal margins and non-linear characteristics. This tutorial discusses the current status and future directions in DRAM-CIM and NVM-CIM research, which address the abovementioned challenge.

关键词： computing-in-memory dynamic random access memory non-volatile memory magnetic random access memory resistive random access memory phase change memory hardware for artificial intelligence

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A CFMB STT-MRAM-Based computing-in-memory Proposal With Cascade computing Unit for Edge AI Devices

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2024年第1期71卷 187-200页

作者： Zhou, Yongliang Zhou, Zixuan Wei, Yiming Yang, Zhen Lin, Xiao Dai, Chenghu Hao, Licai Peng, Chunyu Cai, Hao Wu, Xiulong Anhui Univ Sch Integrated Circuits Hefei 230601 Peoples R China Anhui Prov High Performance Integrated Circuit Eng Hefei 230601 Peoples R China Anhui Prov High Performance Integrated Circuit Eng Hefei 230601 Peoples R China Southeast Univ Sch Elect Sci & Engn Natl ASIC Syst Engn Ctr Nanjing 210000 Peoples R China

The application of non-volatile memory technology is increasingly attractive for computing-in-memory (CIM) owing to high integration density and negligible standby power consumption. This study proposes an spin-transfer-torque (STT) magnetic random access memory (MRAM) based CIM macro which incorporates following innovative features: 1) cross-feedback margin-boost (CFMB) scheme to enable robust and fast reading operations against process variation and limited Tunneling Magnetoresistance Ratio (TMR);2) cascade computing units (CCU) and related design method for efficient and stable multi-bit multiply-and-accumulate (MAC) operation;and 3) dual computing mode scheme and resolution adjustable quantization module to optimize energy efficiency and operating speed. The post-simulations are performed under 28nm CMOS&MTJ technology. The results demonstrate the achievement in energy efficiency of 36.4 TOPS/W while performing MAC operations with up to 16-bit weights, 4-bit inputs, and 22-bit outputs.

关键词： Computer architecture Sensors Transistors Artificial intelligence Tunneling magnetoresistance Threshold voltage Power demand computing-in-memory STT-MRAM cross-feedback margin-boost (CFMB) cascade computing units (CCU) multiply-and-accumulate (MAC)

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