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RDCIM: RISC-V Supported Full-Digital computing-in-memory Processor With High Energy Efficiency and Low Area Overhead

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2024年第4期71卷 1719-1732页

作者： Yi, Wente Mo, Kefan Wang, Wenjia Zhou, Yitong Zeng, Yejun Yuan, Zihan Cheng, Bojun Pan, Biao Beihang Univ Sch Integrated Circuit Sci & Engn Beijing 100191 Peoples R China Hong Kong Univ Sci & Technol Guangzhou Microelect Thrust Funct Hub Guangzhou 510000 Peoples R China

Digital computing-in-memory (DCIM) that merges computing logic into memory has been proven to be an efficient architecture for accelerating multiply-and-accumulates (MACs). However, low energy efficiency and high area overhead pose a primary restriction for integrating DCIM in re-configurable processors required for multi-functional workloads. To alleviate this dilemma, a novel RISC-V supported full-digital computing-in-memory processor (RDCIM) is designed and fabricated with 55nm CMOS technology. In RDCIM, an adding-on-memory-boundary (AOMB) scheme is adopted to improve the energy efficiency of DCIM. Meanwhile, a multi-precision adaptive accumulator (MPAA) and a serial-parallel conversion supported SRAM buffer (SPBUF) are employed to reduce the area overhead caused by the peripheral circuits and the intermediate buffer for multi-precision support. The results show that the energy efficiency in our design is 16.6 TOPS/W (8-bit) and 66.3 TOPS/W (4-bit). Compared to related works, the proposed RDCIM macro shows a maximum energy efficiency improvement of 1.22x in a continuous computing scenario, an area saving of 1.22x in the accumulator, and an area saving of 3.12x in the input buffer. Moreover, in RDCIM, 5 fine-grained RISC-V extended instructions are designed to dynamically adjust the state of DCIM, reaching 1.2x computation efficiency.

关键词： computing-in-memory RISC-V extended instructions re-configurable precision

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A computing-in-memory-Based One-Class Hyperdimensional computing Model for Outlier Detection

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IEEE TRANSACTIONS ON COMPUTERS 2024年第6期73卷 1559-1574页

作者： Wang, Ruixuan Moon, Sabrina Hassan Hu, Xiaobo Sharon Jiao, Xun Reis, Dayane Villanova Univ Dept Elect & Comp Engn Villanova PA 19085 USA Univ S Florida Dept Comp Sci & Engn Tampa FL 33620 USA Univ Notre Dame Dept Comp Sci & Engn Notre Dame IN 46556 USA

In this work, we present ODHD, an algorithm for outlier detection based on hyperdimensional computing (HDC), a non-classical learning paradigm. Along with the HDC-based algorithm, we propose IM-ODHD, a computing-in-memory (CiM) implementation based on hardware/software (HW/SW) codesign for improved latency and energy efficiency. The training and testing phases of ODHD may be performed with conventional CPU/GPU hardware or our IM-ODHD, SRAM-based CiM architecture using the proposed HW/SW codesign techniques. We evaluate the performance of ODHD on six datasets from different application domains using three metrics, namely accuracy, F1 score, and ROC-AUC, and compare it with multiple baseline methods such as OCSVM, isolation forest, and autoencoder. The experimental results indicate that ODHD outperforms all the baseline methods in terms of these three metrics on every dataset for both CPU/GPU and CiM implementations. Furthermore, we perform an extensive design space exploration to demonstrate the tradeoff between delay, energy efficiency, and performance of ODHD. We demonstrate that the HW/SW codesign implementation of the outlier detection on IM-ODHD is able to outperform the GPU-based implementation of ODHD by at least 331.5x889 x in terms of training/testing latency (and on average 14.0x36.9x in terms of training/testing energy consumption).

关键词： Anomaly detection Task analysis Training Testing Software algorithms Forestry Computers Hyperdimensional computing outlier detection computing-in-memory hardware/software codesign

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A Dual-Split 6T SRAM-Based computing-in-memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2019年第11期66卷 4172-4185页

作者： Si, Xin Khwa, Win-San Chen, Jia-Jing Li, Jia-Fang Sun, Xiaoyu Liu, Rui Yu, Shimeng Yamauchi, Hiroyuki Li, Qiang Chang, Meng-Fan Univ Elect Sci & Technol China Inst Integrated Circuits & Syst Chengdu 610054 Sichuan Peoples R China Natl Tsing Hua Univ Dept Elect Engn Hsinchu 30013 Taiwan TSMC Hsinchu 30078 Taiwan Georgia Inst Technol Atlanta GA 30332 USA Synopsys San Francisco CA 94107 USA Fukuoka Inst Technol Fukuoka Fukuoka 8110295 Japan

computing-in-memory (CIM) is a promising approach to reduce the latency and improve the energy efficiency of deep neural network (DNN) artificial intelligence (AI) edge processors. However, SRAM-based CIM (SRAM-CIM) faces practical challenges in terms of area overhead, performance, energy efficiency, and yield against variations in data patterns and transistor performance. This paper employed a circuit-system co-design methodology to develop a SRAM-CIM unit-macro for a binary-based fully connected neural network (FCNN) layer of the DNN AI edge processors. The proposed SRAM-CIM unit-macro supports two binarized neural network models: an XNOR neural network (XNORNN) and a modified binary neural network (MBNN). To achieve compact area, fast access time, robust operations, and high energy-efficiency, our proposed SRAM-CIM uses a split-wordline compact-rule 6T SRAM and circuit techniques, including a dynamic input-aware reference generation (DIARG) scheme, an algorithm-dependent asymmetric control (ADAC) scheme, a write disturb-free (WDF) scheme, and a common-mode-insensitive small offset voltage-mode sensing amplifier (CMI-VSA). A fabricated 65-nm 4-Kb SRAM-CIM unit-macro achieved 2.4- and 2.3-ns product-sum access times for a FCNN layer using XNORNN and MBNN, respectively. The measured maximum energy efficiency reached 30.49 TOPS/W for XNORNN and 55.8 TOPS/W for the MBNN modes.

关键词： Computer architecture Biological neural networks Microprocessors SRAM cells Program processors Random access memory computing-in-memory binarized DNN edge processors artificial intelligence

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A 16.38TOPS and 4.55POPS/W SRAM computing-in-memory Macro for Signed Operands Computation and Batch Normalization Implementation

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2024年第4期71卷 1706-1718页

作者： Qiao, Xin Guo, Qingyu Tang, Xiyuan Song, Jiahao Wei, Renjie Li, Meng Wang, Runsheng Wang, Yuan Peking Univ MPW Ctr Sch Integrated Circuits Key Lab Microelect Devices & Circuits MoE Beijing 100871 Peoples R China Beijing Adv Innovat Ctr Integrated Circuits Beijing 100871 Peoples R China

Edge artificial intelligence applications impose rigorous demands on local hardware to improve throughput and energy efficiency. computing-in-memory (CIM) architectures provide high parallel and energy-efficient solutions to accelerate the multiply-and-accumulate (MAC) operations in neural networks (NNs). While SRAM-based charge-domain CIM is achieving thousands of TOPS/W energy efficiency, it encounters limitations when dealing with full NN model deployments where both activations and weights are signed. This paper proposes an SRAM-based signed batch normalization (BN) CIM macro for supporting efficient bitwise sparse MAC computation with signed operands and BN operations in deep neural networks. The key features of this macro encompass: 1) a multibit weight unit for the optimization of bitstream sparsity and the sign bit computation, 2) a 2b-serial input configuration to increase throughput and the ADC energy amortization, and 3) a quantization-hardware co-design for the BN implementation. Measurement results show that the proposed 28 nm 64 Kb CIM macro achieves 16.38 TOPS throughput and 4.55 POPS/W energy efficiency, both normalized to 1b operands. The test accuracy of CIFAR10 is 92%, based on the ResNet18 model with co-design BN implementation at signed-8b precision activations and weights.

关键词： Common Information Model (computing) Energy efficiency Computational modeling Computational efficiency Voltage Quantization (signal) Capacitors computing-in-memory SRAM neural network signed operation batch normalization

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An Overview of computing-in-memory Circuits With DRAM and NVM

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2024年第3期71卷 1626-1631页

作者： Kim, Sangjin Yoo, Hoi-Jun Korea Adv Inst Sci & Technol Sch Elect Engn Daejeon 34141 South Korea

computing-in-memory (CIM) has emerged as an energy-efficient hardware solution for machine learning and AI. While static random access memory (SRAM)-based CIM has been prevalent, growing attention is directed towards leveraging dynamic random access memory (DRAM) and non-volatile memory (NVM) with its unique characteristics such as high-density and non-volatility. This brief reviews the evolving trends in DRAM and NVM-based CIM, which have faced unique challenges that arise from SRAM despite their advantages. For instance, the DRAM cell's density comes with leakage and refresh issues, impacting efficiency and computing accuracy. NVM-CIM faces computing accuracy challenges of resistance-based computation with low signal margins and non-linear characteristics. This tutorial discusses the current status and future directions in DRAM-CIM and NVM-CIM research, which address the abovementioned challenge.

关键词： computing-in-memory dynamic random access memory non-volatile memory magnetic random access memory resistive random access memory phase change memory hardware for artificial intelligence

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Accuracy Optimization With the Framework of Non-Volatile computing-in-memory Systems

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2022年第2期69卷 518-529页

作者： Huang, Yuxuan He, Yifan Yue, Jinshan Yang, Huazhong Liu, Yongpan Tsinghua Univ Dept Elect Engn Beijing 100084 Peoples R China Chinese Acad Sci Inst Microelect Beijing 100029 Peoples R China

computing-in-memory (CIM) is a new architecture which is more energy-efficient than the Von Neumann architecture due to the fact that it performs calculation in the memory units which can reduce a large amount of data movement. Nowadays, CIM with non-volatile memory (nvCIM), such as resistive random access memory (RRAM), has become a research frontier to further improve computing performance. Recent works mainly explored how to improve the computing performance of nvCIM, but seldom paid attention to the problem of accuracy loss. In this paper, we propose the nvCIM framework, which can systematically analyze the relationship between the classification accuracy of network models and main analog factors. Based on the nvCIM framework, we further provide detailed optimization methods, including RRAM features, array properties, and ADC parameters. The adaptive voltage-controlled SET and pulse-controlled RESET (VSPR) program-verify scheme is proposed to achieve high-resolution RRAM. And the margin enhancement based current-mode sense amplifier (MECSA) and offset reduction based analog-to-digital converter (ORADC) are proposed to improve the accuracy of analog part computing. Experimental results show that the macro-level and system-level energy efficiency is 112.1 TOPS/W and 9.86 TOPS/W respectively with less than 3.51% loss in contrast to the ideal accuracy, which is 2.9x - 25.9x compared to the energy efficiency of existing RRAM based nvCIM accelerators.

关键词： System performance Voltage Nonvolatile memory Common Information Model (computing) Systematics memory management Integrated circuit modeling computing-in-memory RRAM network classification accuracy framework

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A CFMB STT-MRAM-Based computing-in-memory Proposal With Cascade computing Unit for Edge AI Devices

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2024年第1期71卷 187-200页

作者： Zhou, Yongliang Zhou, Zixuan Wei, Yiming Yang, Zhen Lin, Xiao Dai, Chenghu Hao, Licai Peng, Chunyu Cai, Hao Wu, Xiulong Anhui Univ Sch Integrated Circuits Hefei 230601 Peoples R China Anhui Prov High Performance Integrated Circuit Eng Hefei 230601 Peoples R China Anhui Prov High Performance Integrated Circuit Eng Hefei 230601 Peoples R China Southeast Univ Sch Elect Sci & Engn Natl ASIC Syst Engn Ctr Nanjing 210000 Peoples R China

The application of non-volatile memory technology is increasingly attractive for computing-in-memory (CIM) owing to high integration density and negligible standby power consumption. This study proposes an spin-transfer-torque (STT) magnetic random access memory (MRAM) based CIM macro which incorporates following innovative features: 1) cross-feedback margin-boost (CFMB) scheme to enable robust and fast reading operations against process variation and limited Tunneling Magnetoresistance Ratio (TMR);2) cascade computing units (CCU) and related design method for efficient and stable multi-bit multiply-and-accumulate (MAC) operation;and 3) dual computing mode scheme and resolution adjustable quantization module to optimize energy efficiency and operating speed. The post-simulations are performed under 28nm CMOS&MTJ technology. The results demonstrate the achievement in energy efficiency of 36.4 TOPS/W while performing MAC operations with up to 16-bit weights, 4-bit inputs, and 22-bit outputs.

关键词： Computer architecture Sensors Transistors Artificial intelligence Tunneling magnetoresistance Threshold voltage Power demand computing-in-memory STT-MRAM cross-feedback margin-boost (CFMB) cascade computing units (CCU) multiply-and-accumulate (MAC)

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High-Performance STT-MRAM-Based computing-in-memory Scheme Utilizing Data Read Feature

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IEEE TRANSACTIONS ON NANOTECHNOLOGY 2023年 22卷 817-826页

作者： Wu, Bi Liu, Kai Yu, Tianyang Zhu, Haonan Chen, Ke Yan, Chenggang Deng, Erya Liu, Weiqiang Nanjing Univ Aeronaut & Astronaut Coll Elect & Informat Engn Coll Integrated Circuits Nanjing 211106 Peoples R China Minist Ind & Informat Technol Key Lab Aerosp Integrated Circuits & Microsyst Nanjing 211106 Peoples R China

With the development of Artificial Intelligence (AI) and Binary neural networks (BNN), the computing efficiency of the computing system is expected to be much better, however, enormous amounts of data processing have caused an intolerable 'memory wall' and 'power wall' challenge for traditional Von Neumann architectures. Therefore, more advanced computing-in-memory (CiM) architectures are proposed. The emerging non-volatile memory Spin Transfer Torque Magnetic Random Access memory (STT-MRAM), with its fast access speed, near-zero leakage power consumption and high density is one of the most competitive carriers for CiM *** to the inherent read-write asymmetry of STT-MRAM, the read overhead is multiples smaller than the exaggerated write overhead. To better exploit the potential of MRAM, we focus on implementing an CiM based on the reading *** work introduces the principle of CiM and proposes four basic logic operations (XNOR, XOR, AND and OR) based on STT-MRAM. Furthermore, a delay-based XNOR-popcount (XNOR-PC) operation for BNN based on XNOR operation is proposed. Incorporating the reading characteristics of STT-MRAM and slight modifications to the peripheral circuitry, these operations achieve significant optimisation in terms of performance and energy consumption. Simulation results show the proposed scheme can reduce the latency of XOR, AND, and OR operations at least by 99.3%, 82.2% and 80.2% compared with the existing design. The proposed XNOR-PC operation achieves at least a 59.4% reduction in power consumption and has a high degree of reliability. Also, Monte Carlo simulations prove the feasibility and robustness of the schemes.

关键词： computing-in-memory STT-MRAM boolean logics BNN XNOR-PC

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A 768.7-2124.2 TOPS/W Time-Domain computing-in-memory Macro With Low Static Leakage and Precision-Configurable TDC

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2024年第5期71卷 2789-2793页

作者： Xue, Chang Qiao, Xin Ren, Xu Du, Gang Wang, Yuan He, Yandong Peking Univ Sch Integrated Circuits Beijing 100871 Peoples R China Peking Univ Beijing Adv Innovat Ctr Integrated Circuits Beijing 100871 Peoples R China

In always-on edge devices, the static leakage current in weights retention accounts for a significant proportion of power consumption. Furthermore, the analog-to-digital converter (ADC) module consumes a lot of area and power in most computing-in-memory (CIM) architectures. Therefore, this design presents an 8 Kb time-domain (TD) CIM macro with low static leakage. In addition, this brief takes advantage of the scalability of TD-CIM and presents a precision-configurable time-to-digital converter (TDC) applied to scenarios that require adjustable accuracy. It achieves configurable precision of 2 to 4 bits with a multiplication-and-accumulation (MAC) range of 32 in each delay chain. The TDC module accounts for only 2.9% of the total macro area, achieving nearly a tenfold improvement over prior works. The measured normalized energy efficiency is 768.7-2124.2 TOPS/W. The static leakage of the macro is 206 fW/bit while VDD is 1.2 V. This brief achieves 91.1%-86.1% inference accuracy on the CIFAR-10 dataset with 8-bit precision in inputs and weights.

关键词： Random access memory Delays Time-domain analysis SRAM cells Computer architecture Transistors Threshold voltage SRAM computing-in-memory time-domain precision-configurable time-to-digital converter

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An eDRAM-Based computing-in-memory Macro With Full-Valid-Storage and Channel-Wise-Parallelism for Depthwise Neural Network

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2024年第5期71卷 2539-2543页

作者： Qiao, Xin Yang, Youming Xue, Chang He, Yandong Cui, Xiaoxin Jia, Song Wang, Yuan Peking Univ MPW Ctr Sch Integrated Circuits Key Lab Microelect Devices & Circuits Beijing 100871 Peoples R China

computing-in-memory (CIM) provides a highly efficient solution for neural networks in edge artificial intelligence applications. Most SRAM-based CIM designs can achieve high energy efficiency and area efficiency in standard convolutional layer's multiply-and-accumulate (MAC) operations. However, when deploying depthwise separable convolution, they face several challenges. For these CIMs with weight-stationary, the lower activations reuse increases redundant memory reducing area efficiency and the fewer parameters of depthwise convolutional MAC decreases energy efficiency. To address these issues, we propose a depthwise separable convolutional computing-in-memory (DSC-CIM) that supports channel-wise parallel computation to increase area efficiency and energy efficiency. It includes three key techniques: (1) a 5T2C eDRAM bitcell for low power activation update and high area efficiency, (2) an independent update in the column direction to enable horizontal and vertical movement of the convolution window in the feature map, and (3) a data weight configuration circuit (DWCC) that supports both signed and unsigned parameters' MAC operation. Layout post-simulations show that the proposed 28 nm DSC-CIM macro achieves an energy efficiency of 20.13 TOPS/W for 8b parameters on depthwise convolution. The inference accuracy on CIFAR-10 with 8b MobileNet-V2 model is 92.6%.

关键词： computing-in-memory eDRAM depthwise convolution energy efficiency area efficiency

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