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10T SRAM computing-in-memory Macros for Binary and Multibit MAC Operation of DNN Edge Processors

IEEE ACCESS 2021年 9卷 71262-71276页

作者： Nguyen, Van Truong Kim, Jie-Seok Lee, Jong-Wook Kyung Hee Univ Dept Elect & Informat Convergence Engn Informat & Commun Syst Chip SoC Res Ctr Yongin 17104 South Korea Kyung Hee Univ Sch Elect & Informat Dept Elect Yongin 17104 South Korea

computing-in-memory (CIM) is a promising approach to reduce latency and improve the energy efficiency of the multiply-and-accumulate (MAC) operation under a memory wall constraint for artificial intelligence (AI) edge processors. This paper proposes an approach focusing on scalable CIM designs using a new ten-transistor (10T) static random access memory (SRAM) bit-cell. Using the proposed 10T SRAM bit-cell, we present two SRAM-based CIM (SRAM-CIM) macros supporting multibit and binary MAC operations. The first design achieves fully parallel computing and high throughput using 32 parallel binary MAC operations. Advanced circuit techniques such as an input-dependent dynamic reference generator and an input-boosted sense amplifier are presented. Fabricated in 28 nm CMOS process, this design achieves 409.6 GOPS throughput, 1001.7 TOPS/W energy efficiency, and a 169.9 TOPS/mm(2) throughput area efficiency. The proposed approach effectively solves previous problems such as writing disturb, throughput, and the power consumption of an analog to digital converter (ADC). The second design supports multibit MAC operation (4-b weight, 4-b input, and 8-b output) to increase the inference accuracy. We propose an architecture that divides 4-b weight and 4-b input multiplication to four 2-b multiplication in parallel, which increases the signal margin by 16x compared to conventional 4-b multiplication. Besides, the capacitive digital-to-analog converter (CDAC) area issue is effectively addressed using the intrinsic bit-line capacitance existing in the SRAM-CIM architecture. The proposed approach of realizing four 2-b parallel multiplication using the CDAC is successfully demonstrated with a modified LeNet-5 neural network. These results demonstrate that the proposed 10T bit-cell is promising for realizing robust and scalable SRAM-CIM designs, which is essential for realizing fully parallel edge computing.

关键词： Random access memory Throughput Energy efficiency Transistors Program processors Parallel processing Layout computing-in-memory static random access memory deep neural network machine learning edge processor

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High-Performance STT-MRAM-Based computing-in-memory Scheme Utilizing Data Read Feature

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IEEE TRANSACTIONS ON NANOTECHNOLOGY 2023年 22卷 817-826页

作者： Wu, Bi Liu, Kai Yu, Tianyang Zhu, Haonan Chen, Ke Yan, Chenggang Deng, Erya Liu, Weiqiang Nanjing Univ Aeronaut & Astronaut Coll Elect & Informat Engn Coll Integrated Circuits Nanjing 211106 Peoples R China Minist Ind & Informat Technol Key Lab Aerosp Integrated Circuits & Microsyst Nanjing 211106 Peoples R China

With the development of Artificial Intelligence (AI) and Binary neural networks (BNN), the computing efficiency of the computing system is expected to be much better, however, enormous amounts of data processing have caused an intolerable 'memory wall' and 'power wall' challenge for traditional Von Neumann architectures. Therefore, more advanced computing-in-memory (CiM) architectures are proposed. The emerging non-volatile memory Spin Transfer Torque Magnetic Random Access memory (STT-MRAM), with its fast access speed, near-zero leakage power consumption and high density is one of the most competitive carriers for CiM *** to the inherent read-write asymmetry of STT-MRAM, the read overhead is multiples smaller than the exaggerated write overhead. To better exploit the potential of MRAM, we focus on implementing an CiM based on the reading *** work introduces the principle of CiM and proposes four basic logic operations (XNOR, XOR, AND and OR) based on STT-MRAM. Furthermore, a delay-based XNOR-popcount (XNOR-PC) operation for BNN based on XNOR operation is proposed. Incorporating the reading characteristics of STT-MRAM and slight modifications to the peripheral circuitry, these operations achieve significant optimisation in terms of performance and energy consumption. Simulation results show the proposed scheme can reduce the latency of XOR, AND, and OR operations at least by 99.3%, 82.2% and 80.2% compared with the existing design. The proposed XNOR-PC operation achieves at least a 59.4% reduction in power consumption and has a high degree of reliability. Also, Monte Carlo simulations prove the feasibility and robustness of the schemes.

关键词： computing-in-memory STT-MRAM boolean logics BNN XNOR-PC

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A 768.7-2124.2 TOPS/W Time-Domain computing-in-memory Macro With Low Static Leakage and Precision-Configurable TDC

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2024年第5期71卷 2789-2793页

作者： Xue, Chang Qiao, Xin Ren, Xu Du, Gang Wang, Yuan He, Yandong Peking Univ Sch Integrated Circuits Beijing 100871 Peoples R China Peking Univ Beijing Adv Innovat Ctr Integrated Circuits Beijing 100871 Peoples R China

In always-on edge devices, the static leakage current in weights retention accounts for a significant proportion of power consumption. Furthermore, the analog-to-digital converter (ADC) module consumes a lot of area and power in most computing-in-memory (CIM) architectures. Therefore, this design presents an 8 Kb time-domain (TD) CIM macro with low static leakage. In addition, this brief takes advantage of the scalability of TD-CIM and presents a precision-configurable time-to-digital converter (TDC) applied to scenarios that require adjustable accuracy. It achieves configurable precision of 2 to 4 bits with a multiplication-and-accumulation (MAC) range of 32 in each delay chain. The TDC module accounts for only 2.9% of the total macro area, achieving nearly a tenfold improvement over prior works. The measured normalized energy efficiency is 768.7-2124.2 TOPS/W. The static leakage of the macro is 206 fW/bit while VDD is 1.2 V. This brief achieves 91.1%-86.1% inference accuracy on the CIFAR-10 dataset with 8-bit precision in inputs and weights.

关键词： Random access memory Delays Time-domain analysis SRAM cells Computer architecture Transistors Threshold voltage SRAM computing-in-memory time-domain precision-configurable time-to-digital converter

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An eDRAM-Based computing-in-memory Macro With Full-Valid-Storage and Channel-Wise-Parallelism for Depthwise Neural Network

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2024年第5期71卷 2539-2543页

作者： Qiao, Xin Yang, Youming Xue, Chang He, Yandong Cui, Xiaoxin Jia, Song Wang, Yuan Peking Univ MPW Ctr Sch Integrated Circuits Key Lab Microelect Devices & Circuits Beijing 100871 Peoples R China

computing-in-memory (CIM) provides a highly efficient solution for neural networks in edge artificial intelligence applications. Most SRAM-based CIM designs can achieve high energy efficiency and area efficiency in standard convolutional layer's multiply-and-accumulate (MAC) operations. However, when deploying depthwise separable convolution, they face several challenges. For these CIMs with weight-stationary, the lower activations reuse increases redundant memory reducing area efficiency and the fewer parameters of depthwise convolutional MAC decreases energy efficiency. To address these issues, we propose a depthwise separable convolutional computing-in-memory (DSC-CIM) that supports channel-wise parallel computation to increase area efficiency and energy efficiency. It includes three key techniques: (1) a 5T2C eDRAM bitcell for low power activation update and high area efficiency, (2) an independent update in the column direction to enable horizontal and vertical movement of the convolution window in the feature map, and (3) a data weight configuration circuit (DWCC) that supports both signed and unsigned parameters' MAC operation. Layout post-simulations show that the proposed 28 nm DSC-CIM macro achieves an energy efficiency of 20.13 TOPS/W for 8b parameters on depthwise convolution. The inference accuracy on CIFAR-10 with 8b MobileNet-V2 model is 92.6%.

关键词： computing-in-memory eDRAM depthwise convolution energy efficiency area efficiency

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Bit-Aware Fault-Tolerant Hybrid Retraining and Remapping Schemes for RRAM-Based computing-in-memory Systems

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2022年第7期69卷 3144-3148页

作者： Huang, Yuxuan He, Yifan Wang, Jingyu Yue, Jinshan Zhang, Lu Zou, Kaiwei Yang, Huazhong Liu, Yongpan Tsinghua Univ Dept Elect Engn Beijing 100084 Peoples R China Chinese Acad Sci Inst Microelect Beijing 100029 Peoples R China

Non-volatile computing-in-memory (nvCIM) has become one of the most efficient methods to deal with increasingly complicated neural networks compared to the traditional von Neumann architecture. However, due to the immature fabrication issues, the yield of resistive random access memory (RRAM) cells is limited, which causes the Stuck-At-Faults (SAFs) and decrease of network classification accuracy. In this brief, the bit-aware fault-tolerant hybrid retraining and remapping schemes are proposed to restore the network classification accuracy caused by SAFs. The low weight bits are retrained with the fault mask and the high weight bits are remapped with column swap and zero correction methods. For those bits whose values are still wrong after remapping, the fault index is used to record and calibrate. Experimental results show that the classification accuracy of MNIST, CIFAR-10, and CIFAR-100 is restored from 12.54% to 98.13%, from 10.29% to 90.60%, and from 0.94% to 74.30% with only 10.3% energy consumption and 5.88% area overhead, respectively.

关键词： Circuit faults Indexes Fault tolerant systems Hardware Training Software algorithms Inference algorithms computing-in-memory RRAM fault-tolerant bit-aware schemes

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A ReRAM-Based computing-in-memory Convolutional-Macro With Customized 2T2R Bit-Cell for AIoT Chip IP Applications

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2020年第9期67卷 1534-1538页

作者： Tan, Fei Wang, Yiming Yang, Yiming Li, Liran Wang, Tian Zhang, Feng Wang, Xinghua Gao, Jianfeng Liu, Yongpan Beijing Inst Technol Sch Informat & Elect Beijing 100081 Peoples R China Chinese Acad Sci Key Lab Microelect Devices & Integrated Technol Inst Microelect Beijing 100029 Peoples R China Tsinghua Univ Dept Elect Engn Beijing 100084 Peoples R China

To reduce the energy-consuming and time latency incurred by Von Neumann architecture, this brief developed a complete computing-in-memory (CIM) convolutional macro based on ReRAM array for the convolutional layers of a LeNet-like convolutional neural network (CNN). We binarized the input layer and the first convolutional layer to get higher accuracy. The proposed ReRAM-CIM convolutional macro is suitable as an IP core for any binarized neural networks' convolutional layers. This brief customized a bit-cell consisting of 2T2R ReRAM cells, regarded 9 x 8 bit-cells as one unit to achieve high hardware compute accuracy, great read/compute speed, and low power consuming. The ReRAM-CIM convolutional macro achieved 50 ns product-sum computing time for one complete convolutional operation in a convolutional layer in the customized CNN, with an accuracy of 96.96% on MNIST database and a peak energy efficiency of 58.82 TOPS/W.

关键词： ReRAM computing-in-memory AIoT application CNN convolutional layer edge computing artificial intelligence

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An ADC-Less RRAM-Based computing-in-memory Macro With Binary CNN for Efficient Edge AI

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2023年第6期70卷 1871-1875页

作者： Li, Yi Chen, Jia Wang, Linfang Zhang, Woyu Guo, Zeyu Wang, Jun Han, Yongkang Li, Zhi Wang, Fei Dou, Chunmeng Xu, Xiaoxin Yang, Jianguo Wang, Zhongrui Shang, Dashan Chinese Acad Sci Inst Microelect Beijing 100029 Peoples R China Univ Chinese Acad Sci Beijing 100049 Peoples R China ACCESS AI Chip Ctr Emerging Smart Syst InnoHK Ctr Hong Kong Sci Pk Hong Kong Peoples R China Zhejiang Lab Hangzhou 311121 Peoples R China Univ Hong Kong Dept Elect & Elect Engn Hong Kong Peoples R China

Resistive random-access memory (RRAM) based non-volatile computing-in-memory (nvCIM) has been regarded as a promising solution to enable efficient data-intensive artificial intelligence (AI) applications on resource-limited edge systems. However, existing weighted-current summation-based nvCIM suffers from device non-idealities and significant time, storage, and energy overheads when processing high-precision analog signals. To address these issues, we propose a 3T2R digital nvCIM macro for a fully hardware-implemented binary convolutional neural network (HBCNN), focusing on accelerating edge AI applications at low weight precision. By quantizing the voltage-division results of RRAMs through inverters, the 3T2R macro provides a stable rail-to-rail output without analog-to-digital converters or sensing amplifiers. Moreover, both batch normalization and sign activation are integrated on-chip. The hybrid simulation results show that the proposed 3T2R digital macro achieves an 86.2% (95.6%) accuracy on the CIFAR-10 (MNIST) dataset, corresponding to a 4.7% (1.9%) accuracy loss compared to the software baselines, which also feature a peak energy efficiency of 51.3 TOPS/W and a minimum latency of 8 ns, realizing an energy-efficient, low-latency, and robust AI processor.

关键词： Inverters Convolutional neural networks Hardware Software Kernel Resistance Edge computing RRAM hardware-implementation binary CNN computing-in-memory ADC free energy-efficient

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Toggle Rate Aware Quantization Model Based on Digital Floating-Point computing-in-memory Architecture

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2024年第6期71卷 3181-3185页

作者： Chen, Xi Zhao, Yitong Guo, An Chen, Jinwu Dong, Fangyuan Zhang, Zhaoyang Xiong, Tianzhu Wang, Bo Kong, Yuyao Si, Xin Southeast Univ Natl AS Ctr Nanjing 211189 Peoples R China

computing-in-memory (CIM) has been proven to achieve high energy efficiency and significant acceleration effects on neural networks with high computational parallelism. Based on typical integer CIMs, some floating-point CIMs (FP-CIM) are proposed recently to execute more accuracy-demanding tasks such as training and high-precision inference. However, prior research has not adequately explored the relationship between circuit design within the FP-CIM architecture and hardware/software metrics. Furthermore, in digital circuits, the data toggle rate significantly affect hardware performance. In this brief, a toggle rate-aware quantization model is proposed to define and explore the design space of FP-CIM. Based on the experimental results, some key considerations on FP-CIM design are derived. With the toggle rate reduction scheme, toggle rate can be reduced by 28%, resulting in a remarkable 1.18x improvement in energy efficiency with only a 0.35% accuracy loss. To validate our model, a 28nm digital FP-CIM test chip is fabricated which achieves energy efficiency of 32.28 TFLOPS/W and inference accuracy of 76.14% on DenseNet161 and ImageNet dataset.

关键词： Quantization (signal) Measurement Computer architecture Integrated circuit modeling Energy efficiency Computational modeling Space exploration Quantization toggle rate floating-point computing-in-memory

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XNOR-Bitcount Operation Exploiting computing-in-memory With STT-MRAMs

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2023年第3期70卷 1259-1263页

作者： Musello, Ariana Garzon, Esteban Lanuzza, Marco Procel, Luis Miguel Taco, Ramiro Synopsys Chile Ltda Elect Design Automat Grp Santiago 7630229 Chile Univ Calabria Dept Comp Engn Modeling Elect & Syst I-87036 Arcavacata Di Rende Italy Univ San Francisco Quito Inst Micro & Nanoelect Quito 170901 Ecuador

This brief presents an energy-efficient and high-performance XNOR-bitcount architecture exploiting the benefits of computing-in-memory (CiM) and unique properties of spin-transfer torque magnetic RAM (STT-MRAM) based on double-barrier magnetic tunnel junctions (DMTJs). Our work proposes hardware and algorithmic optimizations, benchmarked against a state-of-the-art CiM-based XNOR-bitcount design. Simulation results show that our hardware optimization reduces the storage requirement (-50%) for each XNOR-bitcount operation. The proposed algorithmic optimization improves execution time and energy consumption by about 30% (78%) and 26% (85%), respectively, for single (5 sequential) 9-bit XNOR-bitcount operations. As a case study, our solution is demonstrated for shape analysis using bit-quads.

关键词： Optimization Magnetic tunneling Switches Torque Hardware Transistors Shape computing-in-memory MAC XNOR-bitcount BNN CNN spin-transfer torque STT-MRAM DMTJ bit-quad

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An RRAM-Based Digital computing-in-memory Macro With Dynamic Voltage Sense Amplifier and Sparse-Aware Approximate Adder Tree

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2023年第2期70卷 416-420页

作者： He, Yifan Yue, Jinshan Feng, Xiaoyu Huang, Yuxuan Jia, Hongyang Wang, Jingyu Zhang, Lu Sun, Wenyu Yang, Huazhong Liu, Yongpan Tsinghua Univ Dept Elect Engn Beijing 100084 Peoples R China Chinese Acad Sci Key Lab Microelect Devices & Integrated Technol Inst Microelect Beijing 100029 Peoples R China Tsinghua Shenzhen Int Grad Sch Shenzhen 518000 Peoples R China

RRAM is a promising candidate to implement large-capacity in-memory computing on edge AI devices due to its high density. However, the efficiency and accuracy of RRAM-based computing-in-memory (CIM) works are limited by large accumulation currents and device variations. The SRAM-based digital CIM achieves superior performance and efficiency while the adder tree dominates the area. In this brief, a digital RRAM CIM macro is proposed to achieve a better trade-off between accuracy, energy, and performance by three techniques. First, a dynamic voltage sense amplifier is designed to reduce > 90% read currents of low resistance state (LRS) cell. Second, an OR gate approximate adder tree is proposed to reduce the area of the adder tree by 40%. Third, a sparse-aware finetuning algorithm is proposed to reduce the accuracy loss of approximate arithmetic to 0.4% on Cifar-10 dataset. The proposed design achieves 1966TOPS/W energy efficiency and 51.2GOPS/Kb normalized throughput at 1-bit precision which is 1.2x and 1.8x higher than previous RRAM-based designs. This brief demonstrates the advantage of digital CIM using RRAM devices.

关键词： Adders Voltage Logic gates Neural networks Computer architecture Sensors Resistance computing-in-memory RRAM Approximate computing energy efficiency neural network sparsity

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