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Array-level boosting method with spatial extended allocation to improve the accuracy of memristor based computing-in-memory chips

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Science China(Information Sciences) 2021年第6期64卷 80-88页

作者： Wenqiang ZHANG Bin GAO Peng YAO Jianshi TANG He QIAN Huaqiang WU Institute of Microelectronics Beijing National Research Center for Information Science and Technology (BNRist)Tsinghua University Institute of Microelectronics Beijing National Research Center for Information Science and Technology (BNRist)Tsinghua University

Memristor based computing-in-memory chips have shown the potentials to accelerate deep neural networks with high energy efficiency. Due to the inherent filament-based conductive mechanism of the memristor, the reading and writing noises are hard to eliminate. Besides, the precision of the large-scale memristor array is still limited. However, when the noise of the memristor is large, the existing training methods to reduce the accuracy loss of memristor based computing-in-memory chips will face ***, we proposed the array-level boosting method with spatial extended allocation to reduce the accuracy loss induced by the limited precision and large noises. To optimize the spatial allocation number of each layer in the neural network, the greedy spatial extended allocation algorithm is also proposed. The image processing and classification tasks are demonstrated based on fabricated 32×128 memristor arrays to valid the performance of the proposed method. The chip-in-loop results show that the recovered accuracy of ResNet-34 on CIFAR-10 with array-level boosting method is 92.3%, which is closed to software-based accuracy of 93.2%.

关键词： memristor computing-in-memory array-level boosting neuromorphic computing RRAM

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computing-in-memory with Ferroelectric Materials and Beyond

Computing-in-Memory with Ferroelectric Materials and Beyond

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International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT)

作者： Lu, Darsen D. Natl Cheng Kung Univ Inst Microelect Dept Elect Engn Tainan Taiwan

ISBN: (纸本)9798350334166

Recent discovery of hafnium-based ferroelectric (FE) materials opens up numerous CMOS-compatible memory device opportunities: FE capacitors, FE-FETs, and FE tunnel junctions. These devices offer significant advantages in endurance, write speed, and power compared to today's flash. In this paper, we give a brief overview of FE materials/devices fundamentals, and its applicability towards computing-inmemory (CIM). We discuss CIM realized using FE-FinFET arrays with various possible configurations. Alternatively, FE capacitors in CMOS backend may be used in non-volatile SRAM cells to store contents of CIM-SRAM before powering off. We also present CIMulator, a simulation platform to account for device, circuit, and neural network aspects CIM macros with deep machine learning applications.

关键词： ferroelectric materials computing-in-memory non-volatile SRAM FinFET

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A Robust 8-Bit Non-Volatile computing-in-memory Core for Low-Power Parallel MAC Operations

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2020年第6期67卷 1867-1880页

作者： Zhang, Sai Huang, Kejie Shen, Haibin Zhejiang Univ Coll Informat Sci & Elect Engn Hangzhou 310058 Peoples R China

The Artificial Intelligence (AI) in edge computing is requesting new processing units with a much higher computing-power ratio. The emerging resistive Non-Volatile memory (NVM) with the in-memory computing capability may greatly advance the AI hardware technologies. In this paper, we propose the use of binary resistive memory to form an 8-bit fixed-point data/weight for AI computing. A robust computing-in-memory (CIM) core with digital input and analog output Multiplication-and-Accumulation (MAC) circuit is proposed. The corresponding integration scheme and Successive Approximation Register Analog-to-Digital Converter (SAR ADC) based data conversion scheme are also presented. The simulation results show that the proposed CIM core achieves 7.26 bit of Effective Number of Bits (ENOB) with 0.78mW (256*1) power consumption and 1.85M/s computing speed. Compared with previously reported CIM implementations and Deep Learning Accelerators (DLAs) (without CIM ability), our design achieves 2.23-7.26x better energy efficiency in 8-bit input 8-bit weight pattern, and achieves relatively high accuracy with LeNet and AlexNet.

关键词： Nonvolatile memory Artificial intelligence Random access memory Common Information Model (computing) Robustness Computer architecture Common Information Model (electricity) Non-volatile memory multiplication-and-accumulation computing-in-memory resistive random access memory (RRAM) integral multiplier capacitors-shared SAR ADC

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An Energy-Efficient computing-in-memory (CiM) Scheme Using Field-Free Spin-Orbit Torque (SOT) Magnetic RAMs

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IEEE TRANSACTIONS ON EMERGING TOPICS IN computing 2023年第2期11卷 331-342页

作者： Wu, Bi Zhu, Haonan Reis, Dayane Wang, Zhaohao Wang, Ying Chen, Ke Liu, Weiqiang Lombardi, Fabrizio Hu, Xiaobo Sharon Nanjing Univ Aeronaut & Astronaut Coll Elect & Informat Engn Nanjing 211106 Peoples R China Minist Ind & Informat Technol Key Lab Aerosp Integrated Circuits & Microsyst Nanjing 211106 Peoples R China Univ Notre Dame Dept Comp Sci & Engn Notre Dame IN 46656 USA Univ S Florida Dept Comp Sci & Engn Tampa FL 33620 USA Beihang Univ Fert Beijing Res Inst Beijing Adv Innovat Ctr Big Data & Brain Comp Sch Integrated Circuit Sci & Engn Beijing 100191 Peoples R China Chinese Acad Sci Inst Comp Technol Beijing 100190 Peoples R China Northeastern Univ Dept Elect & Comp Engn Boston MA 02115 USA

The separation of memory and computing units in the von Neumann architecture leads to undesirable energy consumption due to data movement and insufficient memory bandwidth. Energy-efficient in-memory computing platforms have the potential to address such issues. Due to its non-volatility and advantageous features over CMOS (such as low power, near-zero leakage current and high integration density), spin-based devices have been advocated for in-memory computing. This paper proposes a field-free Spin Orbit Torque (FF-SOT) MRAM based computing-in-memory (CiM) scheme that realizes XNOR/XOR logic and a cascading adder. This novel FF-SOT-CiM design does not require expensive peripheral circuits for computation while using the same memory cell design as a SOT-MRAM. Furthermore, FF-SOT-CiM does not require additional write cycles to save the result of its computations in the memory. The design offers higher write speed and;lower operating energy compared to CiM schemes based on other technologies;it also alleviates the source degeneration effect by leveraging an advanced switching mechanism. Extensive simulation results show that the proposed FF-SOT-CiM achieves up to 3.1x (2.6x) latency (energy) reduction compared to SRAM-based CiM, with negligible hardware overhead when performing in-memory XOR. ADD operations;the proposed FF-SOT-CiM can be to 5.0X and 1.5X faster and 3.4X and 1.1X more energy efficient than existing STT-based and FeFET-based schemes, respectively.

关键词： Random access memory Magnetic tunneling Switches Torque Microprocessors Adders Simulation computing-in-memory full adder magnetic random access memory spin orbit torque (SOT) XNOR/XOR

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RDCIM: RISC-V Supported Full-Digital computing-in-memory Processor With High Energy Efficiency and Low Area Overhead

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2024年第4期71卷 1719-1732页

作者： Yi, Wente Mo, Kefan Wang, Wenjia Zhou, Yitong Zeng, Yejun Yuan, Zihan Cheng, Bojun Pan, Biao Beihang Univ Sch Integrated Circuit Sci & Engn Beijing 100191 Peoples R China Hong Kong Univ Sci & Technol Guangzhou Microelect Thrust Funct Hub Guangzhou 510000 Peoples R China

Digital computing-in-memory (DCIM) that merges computing logic into memory has been proven to be an efficient architecture for accelerating multiply-and-accumulates (MACs). However, low energy efficiency and high area overhead pose a primary restriction for integrating DCIM in re-configurable processors required for multi-functional workloads. To alleviate this dilemma, a novel RISC-V supported full-digital computing-in-memory processor (RDCIM) is designed and fabricated with 55nm CMOS technology. In RDCIM, an adding-on-memory-boundary (AOMB) scheme is adopted to improve the energy efficiency of DCIM. Meanwhile, a multi-precision adaptive accumulator (MPAA) and a serial-parallel conversion supported SRAM buffer (SPBUF) are employed to reduce the area overhead caused by the peripheral circuits and the intermediate buffer for multi-precision support. The results show that the energy efficiency in our design is 16.6 TOPS/W (8-bit) and 66.3 TOPS/W (4-bit). Compared to related works, the proposed RDCIM macro shows a maximum energy efficiency improvement of 1.22x in a continuous computing scenario, an area saving of 1.22x in the accumulator, and an area saving of 3.12x in the input buffer. Moreover, in RDCIM, 5 fine-grained RISC-V extended instructions are designed to dynamically adjust the state of DCIM, reaching 1.2x computation efficiency.

关键词： computing-in-memory RISC-V extended instructions re-configurable precision

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A 16.38TOPS and 4.55POPS/W SRAM computing-in-memory Macro for Signed Operands Computation and Batch Normalization Implementation

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2024年第4期71卷 1706-1718页

作者： Qiao, Xin Guo, Qingyu Tang, Xiyuan Song, Jiahao Wei, Renjie Li, Meng Wang, Runsheng Wang, Yuan Peking Univ MPW Ctr Sch Integrated Circuits Key Lab Microelect Devices & Circuits MoE Beijing 100871 Peoples R China Beijing Adv Innovat Ctr Integrated Circuits Beijing 100871 Peoples R China

Edge artificial intelligence applications impose rigorous demands on local hardware to improve throughput and energy efficiency. computing-in-memory (CIM) architectures provide high parallel and energy-efficient solutions to accelerate the multiply-and-accumulate (MAC) operations in neural networks (NNs). While SRAM-based charge-domain CIM is achieving thousands of TOPS/W energy efficiency, it encounters limitations when dealing with full NN model deployments where both activations and weights are signed. This paper proposes an SRAM-based signed batch normalization (BN) CIM macro for supporting efficient bitwise sparse MAC computation with signed operands and BN operations in deep neural networks. The key features of this macro encompass: 1) a multibit weight unit for the optimization of bitstream sparsity and the sign bit computation, 2) a 2b-serial input configuration to increase throughput and the ADC energy amortization, and 3) a quantization-hardware co-design for the BN implementation. Measurement results show that the proposed 28 nm 64 Kb CIM macro achieves 16.38 TOPS throughput and 4.55 POPS/W energy efficiency, both normalized to 1b operands. The test accuracy of CIFAR10 is 92%, based on the ResNet18 model with co-design BN implementation at signed-8b precision activations and weights.

关键词： Common Information Model (computing) Energy efficiency Computational modeling Computational efficiency Voltage Quantization (signal) Capacitors computing-in-memory SRAM neural network signed operation batch normalization

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A computing-in-memory-Based One-Class Hyperdimensional computing Model for Outlier Detection

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IEEE TRANSACTIONS ON COMPUTERS 2024年第6期73卷 1559-1574页

作者： Wang, Ruixuan Moon, Sabrina Hassan Hu, Xiaobo Sharon Jiao, Xun Reis, Dayane Villanova Univ Dept Elect & Comp Engn Villanova PA 19085 USA Univ S Florida Dept Comp Sci & Engn Tampa FL 33620 USA Univ Notre Dame Dept Comp Sci & Engn Notre Dame IN 46556 USA

In this work, we present ODHD, an algorithm for outlier detection based on hyperdimensional computing (HDC), a non-classical learning paradigm. Along with the HDC-based algorithm, we propose IM-ODHD, a computing-in-memory (CiM) implementation based on hardware/software (HW/SW) codesign for improved latency and energy efficiency. The training and testing phases of ODHD may be performed with conventional CPU/GPU hardware or our IM-ODHD, SRAM-based CiM architecture using the proposed HW/SW codesign techniques. We evaluate the performance of ODHD on six datasets from different application domains using three metrics, namely accuracy, F1 score, and ROC-AUC, and compare it with multiple baseline methods such as OCSVM, isolation forest, and autoencoder. The experimental results indicate that ODHD outperforms all the baseline methods in terms of these three metrics on every dataset for both CPU/GPU and CiM implementations. Furthermore, we perform an extensive design space exploration to demonstrate the tradeoff between delay, energy efficiency, and performance of ODHD. We demonstrate that the HW/SW codesign implementation of the outlier detection on IM-ODHD is able to outperform the GPU-based implementation of ODHD by at least 331.5x889 x in terms of training/testing latency (and on average 14.0x36.9x in terms of training/testing energy consumption).

关键词： Anomaly detection Task analysis Training Testing Software algorithms Forestry Computers Hyperdimensional computing outlier detection computing-in-memory hardware/software codesign

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Accuracy Optimization With the Framework of Non-Volatile computing-in-memory Systems

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2022年第2期69卷 518-529页

作者： Huang, Yuxuan He, Yifan Yue, Jinshan Yang, Huazhong Liu, Yongpan Tsinghua Univ Dept Elect Engn Beijing 100084 Peoples R China Chinese Acad Sci Inst Microelect Beijing 100029 Peoples R China

computing-in-memory (CIM) is a new architecture which is more energy-efficient than the Von Neumann architecture due to the fact that it performs calculation in the memory units which can reduce a large amount of data movement. Nowadays, CIM with non-volatile memory (nvCIM), such as resistive random access memory (RRAM), has become a research frontier to further improve computing performance. Recent works mainly explored how to improve the computing performance of nvCIM, but seldom paid attention to the problem of accuracy loss. In this paper, we propose the nvCIM framework, which can systematically analyze the relationship between the classification accuracy of network models and main analog factors. Based on the nvCIM framework, we further provide detailed optimization methods, including RRAM features, array properties, and ADC parameters. The adaptive voltage-controlled SET and pulse-controlled RESET (VSPR) program-verify scheme is proposed to achieve high-resolution RRAM. And the margin enhancement based current-mode sense amplifier (MECSA) and offset reduction based analog-to-digital converter (ORADC) are proposed to improve the accuracy of analog part computing. Experimental results show that the macro-level and system-level energy efficiency is 112.1 TOPS/W and 9.86 TOPS/W respectively with less than 3.51% loss in contrast to the ideal accuracy, which is 2.9x - 25.9x compared to the energy efficiency of existing RRAM based nvCIM accelerators.

关键词： System performance Voltage Nonvolatile memory Common Information Model (computing) Systematics memory management Integrated circuit modeling computing-in-memory RRAM network classification accuracy framework

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A CFMB STT-MRAM-Based computing-in-memory Proposal With Cascade computing Unit for Edge AI Devices

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2024年第1期71卷 187-200页

作者： Zhou, Yongliang Zhou, Zixuan Wei, Yiming Yang, Zhen Lin, Xiao Dai, Chenghu Hao, Licai Peng, Chunyu Cai, Hao Wu, Xiulong Anhui Univ Sch Integrated Circuits Hefei 230601 Peoples R China Anhui Prov High Performance Integrated Circuit Eng Hefei 230601 Peoples R China Anhui Prov High Performance Integrated Circuit Eng Hefei 230601 Peoples R China Southeast Univ Sch Elect Sci & Engn Natl ASIC Syst Engn Ctr Nanjing 210000 Peoples R China

The application of non-volatile memory technology is increasingly attractive for computing-in-memory (CIM) owing to high integration density and negligible standby power consumption. This study proposes an spin-transfer-torque (STT) magnetic random access memory (MRAM) based CIM macro which incorporates following innovative features: 1) cross-feedback margin-boost (CFMB) scheme to enable robust and fast reading operations against process variation and limited Tunneling Magnetoresistance Ratio (TMR);2) cascade computing units (CCU) and related design method for efficient and stable multi-bit multiply-and-accumulate (MAC) operation;and 3) dual computing mode scheme and resolution adjustable quantization module to optimize energy efficiency and operating speed. The post-simulations are performed under 28nm CMOS&MTJ technology. The results demonstrate the achievement in energy efficiency of 36.4 TOPS/W while performing MAC operations with up to 16-bit weights, 4-bit inputs, and 22-bit outputs.

关键词： Computer architecture Sensors Transistors Artificial intelligence Tunneling magnetoresistance Threshold voltage Power demand computing-in-memory STT-MRAM cross-feedback margin-boost (CFMB) cascade computing units (CCU) multiply-and-accumulate (MAC)

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Extreme Partial-Sum Quantization for Analog computing-in-memory Neural Network Accelerators

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ACM JOURNAL ON EMERGING TECHNOLOGIES IN computing SYSTEMS 2022年第4期18卷 1–19页

作者： Kim, Yulhwa Kim, Hyungjun Kim, Jae-Joon Pohang Univ Sci & Technol 77 Cheongam Ro Pohang 37673 Gyeongsangbuk D South Korea Seoul Natl Univ 1 Gwanak Ro Seoul 08826 South Korea

In Analog computing-in-memory (CIM) neural network accelerators, analog-to-digital converters (ADCs) are required to convert the analog partial sums generated from a CIM array to digital values. The overhead from ADCs substantially degrades the energy efficiency of CIM accelerators so that previous works attempted to lower the ADC resolution considering the distribution of the partial sums. Despite the efforts, the required ADC resolution still remains relatively high. In this article, we propose the data-driven partial sum quantization scheme, which exhaustively searches for the optimal quantization range with little computational burden. We also report that analyzing the characteristics of the partial sum distributions at each layer gives an additional information to further reduce the ADC resolution compared to previous works that mostly used the characteristics of the partial sum distributions of the entire network. Based on the finer-level data-driven approach combined with retraining, we present a methodology for extreme partial-sum quantization. Experimental results show that the proposed method can reduce the ADC resolution to 2 to 3 bits for CIFAR-10 dataset, which is the smaller ADC bit resolution than any previous CIM-based NN accelerators.

关键词： computing-in-memory processing-in-memory neural networks analog computing

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