检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

107 篇 期刊文献
73 篇 会议
2 篇 学位论文

馆藏范围

182 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

175 篇 工学
- 133 篇 电气工程
- 80 篇 计算机科学与技术...
- 28 篇 材料科学与工程（可...
- 18 篇 软件工程
- 17 篇 控制科学与工程
- 15 篇 电子科学与技术（可...
- 10 篇 信息与通信工程
- 8 篇 机械工程
- 5 篇 仪器科学与技术
- 3 篇 生物医学工程（可授...
- 2 篇 化学工程与技术
- 1 篇 光学工程
23 篇 理学
- 23 篇 物理学
- 5 篇 化学
11 篇 管理学
- 11 篇 管理科学与工程(可...

主题

182 篇 computing-in-mem...
22 篇 computer archite...
16 篇 random access me...
16 篇 energy efficienc...
15 篇 artificial intel...
15 篇 sram
14 篇 rram
12 篇 reram
12 篇 neural network
11 篇 memristor
11 篇 common informati...
10 篇 transistors
9 篇 edge computing
8 篇 neural networks
8 篇 hardware
8 篇 non-volatile mem...
7 篇 stt-mram
7 篇 voltage
7 篇 logic gates
7 篇 microprocessors

机构

11 篇 univ chinese aca...
11 篇 chinese acad sci...
8 篇 tsinghua univ de...
7 篇 beihang univ sch...
6 篇 peking univ sch ...
4 篇 natl tsing hua u...
4 篇 minist ind & inf...
4 篇 peking univ inst...
4 篇 natl taiwan univ...
4 篇 natl tsing hua u...
3 篇 natl tsing hua u...
3 篇 chinese acad sci...
3 篇 fudan univ sch m...
3 篇 hanyang univ div...
3 篇 beijing adv inno...
3 篇 zhejiang univ co...
3 篇 univ sci & techn...
3 篇 anhui univ sch i...
2 篇 penn state univ ...
2 篇 tsinghua univ el...

作者

15 篇 liu yongpan
14 篇 yang huazhong
12 篇 chang meng-fan
10 篇 yue jinshan
9 篇 li xueqing
8 篇 zhao weisheng
7 篇 tang wenjun
7 篇 dou chunmeng
6 篇 reis dayane
6 篇 kang wang
6 篇 si xin
6 篇 wang linfang
5 篇 yoo hoi-jun
5 篇 shang dashan
5 篇 kim sangjin
5 篇 huang yuxuan
5 篇 liu qi
5 篇 zhang feng
5 篇 bai jinyu
5 篇 tang kea-tiong

语言

179 篇 英文
2 篇 其他
1 篇 中文

检索条件"主题词=Computing-in-memory"

共 182 条记录，以下是51-60 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Sparsity-Aware Clamping Readout Scheme for High Parallelism and Low Power Nonvolatile computing-in-memory based on Resistive memory 53

Sparsity-Aware Clamping Readout Scheme for High Parallelism ...

引用

IEEE International Symposium on Circuits and Systems (IEEE ISCAS)

作者： Wang, Linfang Ye, Wang An, Junjie Dou, Chunmeng Liu, Qi Chang, Meng-Fan Liu, Ming Chinese Acad Sci Inst Microelect Beijing Peoples R China Fudan Univ Shanghai Peoples R China Natl Tsing Hua Univ Hsinchu Taiwan Univ Chinese Acad Sci Beijing Peoples R China

ISBN: (纸本)9781728192017

The input parallelism of resistive memory (RRAM) based nonvolatile computing-in-memory (nvCIM) structure is limited by the signal margin as well as the readout precision. In this work, we propose a sparsity-aware clamping (SAC) scheme and its circuit implementation for nvCIM by co-design of circuit and algorithm. It can adaptively tune the quantized range and resolution of the readout circuit according to the degree of sparsity in neural network models. As a result, the SAC scheme can effectively increase the input parallelism of nvCIMs without incurring degradation on the signal margin or increasing the hardware cost for analogue readout. A case study on processing a multi-layer perceptron (MLP) model with the proposed nvCIM structure shows that the SAC scheme can improve the throughput by 2 times and increase the energy efficiency by 25.35% with negligible inference accuracy loss.

关键词： Resistive memory computing-in-memory Circuit-and-algorithm codesign Sparsity Dynamic clamping

来源：评论

学校读者我要写书评

暂无评论

Considerations of Integrating computing-in-memory and Processing-In-Sensor into Convolutional Neural Network Accelerators for Low-Power Edge Devices 39

Considerations of Integrating Computing-In-Memory and Proces...

引用

39th Symposium on VLSI Technology / 33rd Symposium on VLSI Circuits

作者： Tang, Kea-Tiong Wei, Wei-Chen Yeh, Zuo-Wei Hsu, Tzu-Hsiang Chiu, Yen-Cheng Xue, Cheng-Xin Kuo, Yu -Chun Wen, Tai-Hsing Ho, Mon-Shu Lo, Chung-Chuan Liu, Ren-Shuo Hsieh, Chih-Cheng Chang, Meng-Fan Natl Tsing Hua Univ Hsinchu Taiwan Natl Chung IIsin Univ Taichung Taiwan

ISBN: (纸本)9784863487185

In quest to execute emerging deep learning algorithms at edge devices, developing low-power and low-latency deep learning accelerators (DLAs) have become top priority. To achieve this goal, data processing techniques in sensor and memory utilizing the array strucure have drawn much mention, Processing-in-sensor (PIS) solutions could reduce data transfer;computing-in-memory (CIM) macros could reduce memory access and intermediate data movement. We propose a new architecture to integrate PIS and CIM to realize low-power DLA. The advantages of using these techniques and the challenges from system point-of-view are discussed.

关键词： Deep learning accelerator computing-in-memory processing-in-sensor artificial intelligence

来源：评论

学校读者我要写书评

暂无评论

CIM-KF: Efficient computing-in-memory Circuits for Full-Process Execution of Kalman Filter Algorithm 24

CIM-KF: Efficient Computing-in-memory Circuits for Full-Proc...

引用

53rd International Conference on Parallel Processing (ICPP)

作者： Xiao, Pingdan Hong, Qinghui Du, Sichun Zhang, Jiliang Hunan Univ Changsha Peoples R China

ISBN: (纸本)9798400717932

Kalman Filter (KF) algorithm, which can solve the state estimation problem of multi-variable and complex dynamical system, plays a pivotal role in a multitude of engineering scenarios. However, the traditional digital computing architecture represented by the vonNeumann architecture are currently confronted with high overhead challenges in terms of latency, energy, and area when executing KF algorithm. Aiming at the problem, we propose CIM-KF, the first computing-in-memory (CIM) circuits for KF algorithm. CIMKF can efficiently carry out the entire process of KF algorithm by capitalizing on the large-scale parallel computation inherent in the CIM architecture. The evaluation shows that CIM-KF has average 96.15% accuracy for 32-th order parameter matrix in KF algorithm, and can be 13.89x similar to 55.21x faster than existing ASIC and FPGA implementations of KF algorithm. The results also demonstrate that CIM-KF can deliver up to 3.52x energy efficiency improvement and 54.79x area efficiency improvement, and reduce over 90% latency overhead, compared with the SOTA counterparts. Furthermore, we propose a novel design of ReRAM-CIM architecture, underpinned by the CIM-KF, aimed at precise and rapid calculation of the state of capacity and terminal voltage in Battery Management Systems. By evaluation, our proposed architecture boasts the estimation accuracy within 2% error for the individual battery cell of state of capacity and terminal voltage. With the strengths of the parallel computing intrinsic to CIM architecture and the speed of analog circuit, our architecture facilitates speed up to 70.6x in accurate estimation when bench-marked against the SOTA work.

关键词： computing-in-memory ReRAM Circuit design Kalman Filter algorithm

来源：评论

学校读者我要写书评

暂无评论

Challenges in Circuit Designs of Nonvolatile-memory based computing-in-memory for AI Edge Devices 16

Challenges in Circuit Designs of Nonvolatile-memory based co...

引用

16th International System-on-Chip Design Conference (ISOCC)

作者： Xue, Cheng-Xin Chang, Meng-Fan Natl Tsing Hua Univ Dept Elect Engn Hsinchu Taiwan

ISBN: (纸本)9781728124780

The "memory wall" imposed by the von-Neumann computer architecture limits the bandwidth between the processor and memory, thereby imposing a critical bottleneck in system performance. Emerging memory devices can be used in memory macros as well as computing-in-memory for the Internet of Things (IoT) and artificial intelligence (AI) chips. In this paper, we discuss the challenges involved in the further development of nonvolatile-memory based computing-in-memory for loT and AI chips.

关键词： Artificial intelligence Nonvolatile-memory NVM computing-in-memory CIM nvCIM

来源：评论

学校读者我要写书评

暂无评论

Hierarchical Non-Structured Pruning for computing-in-memory Accelerators with Reduced ADC Resolution Requirement

Hierarchical Non-Structured Pruning for Computing-In-Memory ...

引用

Design, Automation and Test in Europe Conference and Exhibition (DATE)

作者： Xue, Wenlu Bai, Jinyu Sun, Sifan Kang, Wang Beihang Univ Sch Integrated Circuit Sci & Engn Beijing 100191 Peoples R China

ISBN: (纸本)9798350396249

The crossbar architecture, which is comprised of novel nano-devices, enables high-speed and energy-efficient computing-in-memory (CIM) for neural networks. However, the overhead from analog-to-digital converters (ADCs) substantially degrades the energy efficiency of CIM accelerators. In this paper, we introduce a hierarchical non-structured pruning strategy where value-level and bit-level pruning are performed jointly on neural networks to reduce the resolution of ADCs by using the famous alternating direction method of multipliers (ADMM). To verify the effectiveness, we deployed the proposed method to a variety of state-of-the-art convolutional neural networks on two image classification benchmark datasets: CIFAR10, and ImageNet. The results show that our pruning method can reduce the required resolution of ADCs to 2 or 3 bits with only slight accuracy loss (similar to 0.25%), and thus can improve the hardware efficiency by 180%.

关键词： computing-in-memory neural network partial sum pruning alternative direction method of multipliers(ADMM)

来源：评论

学校读者我要写书评

暂无评论

A 2.53μW/channel Event-Driven Neural Spike Sorting Processor with Sparsity-Aware computing-in-memory Macros 56

A 2.53μW/channel Event-Driven Neural Spike Sorting Processo...

引用

56th IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Jiang, Hao Zheng, Jiapei Wang, Yunzhengmao Zhang, Jinshan Zhu, Haozhe Lyu, Liangjian Chen, Yingping Chen, Chixiao Liu, Qi Fudan Univ Frontier Inst Chip & Syst State Key Lab Integrated Chips & Syst Shanghai Peoples R China East China Normal Univ Sch Commun & Elect Engn Shanghai Peoples R China

ISBN: (纸本)9781665451093

Spike sorting processors with high energy efficiency are widely used in large-scale neural signal processing tasks to monitor the activity of neurons in brains. This paper presents a low-power processor for high-accuracy spike sorting and onchip incremental learning using an algorithm-hardware co-design approach. The processor introduces an event-driven mechanism with adaptive-threshold detection to conditionally activate the system in order to reduce power consumption. Sparsity-aware computing-in-memory (CIM) macros are also developed in our design to store templates and perform complicated computations efficiently. The prototype is designed using 28nm technology with an area of 0.018 mm(2)/channel and an overall power efficiency of 2.53 mu W/channel and 84nW/(channel center dot cluster) at the voltage of 0.72V. Moreover, the accuracy of the whole design can reach 94.5% in a 32-channel scenario.

关键词： spike sorting template matching on-chip learning event-driven adaptive threshold computing-in-memory sparsity low power

来源：评论

学校读者我要写书评

暂无评论

Design Framework for SRAM-Based computing-in-memory Edge CNN Accelerators 53

Design Framework for SRAM-Based Computing-In-Memory Edge CNN...

引用

IEEE International Symposium on Circuits and Systems (IEEE ISCAS)

作者： Wang, Yimin Zou, Zhuo Zheng, Lirong Fudan Univ Shanghai Peoples R China

ISBN: (纸本)9781728192017

This paper presents an architectural framework and an evaluation model for Static Random Access memory (SRAM)-based computing-in-memory (CIM) edge Convolutional Neural Network (CNN) accelerators. To provide a baseline for system-level design perspectives, an architectural framework for SRAM-CIM design concerning the key design points in state-of-the-art works is proposed. Furthermore, a configurable evaluation model featuring top-down design flow based on the proposed framework is established to investigate design space explorations. Case studies validated the framework and evaluation model using LeNet-5, AlexNet and VGG-16 to achieve energy-aware optimizations. The optimized memory scale for LeNet-5 is "16 PEs and 120 tiles" with the minimal estimated inference energy of 0.0018 mu J, while for AlexNet and VGG-16, "16 PEs and 120 tiles" is better achieving minimal energy consumption of 0.1733mJ and 0.6825mJ respectively. Estimation results highlight tradeoffs among data representtation parameters and memory partitioning parameters. This work provides specific SRAM-CIM design guidelines from a system-level perspective.

关键词： computing-in-memory SRAM edge computing CNN

来源：评论

学校读者我要写书评

暂无评论

T-EAP: Trainable Energy-Aware Pruning for NVM-based computing-in-memory Architecture 4

T-EAP: Trainable Energy-Aware Pruning for NVM-based Computin...

引用

IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) - Intelligent Technology in the Post-Pandemic Era

作者： Chang, Cheng-Yang Chuang, Yu-Chuan Chou, Kuang-Chao Wu, An-Yeu Natl Taiwan Univ Grad Inst Elect Engn Taipei Taiwan

ISBN: (数字)9781665409964

ISBN: (纸本)9781665409964

While convolutional neural networks (CNNs) are desired for outstanding performance in many applications, the energy consumption for inference becomes enormous. computing-in-memory architecture based on embedded nonvolatile memory (NVM-CIM) has emerged to improve CNNs' energy efficiency. Recently, NVM crossbar-aware pruning has been extensively studied. However, directly incorporating energy estimation during sparse learning has not been well explored. In this paper, for the first time, we propose T-EAP, a trainable energy-aware pruning method to close the gap between pruning policy and energy optimization for NVM-CIM. Specifically, T-EAP improves the energy-accuracy trade-off by removing redundant weight groups that consume significant energy. Moreover, the trainable thresholds enable end-to-end sparse learning without a laborious train-prune-retrain process. Experimental results based on NeuroSim, which is a circuit-level simulator for CIM systems, show that compared with prior work, T-EAP maintains the accuracy while reducing energy consumption by up to 26.5% and 22.7% for VGG-8 and ResNet-20, respectively. We also provide a layer-wise analysis for energy savings to validate the effectiveness of T-EAP.

关键词： computing-in-memory embedded nonvolatile memory deep learning accelerator energy consumption pruning

来源：评论

学校读者我要写书评

暂无评论

C²IM: A Compact computing-in-memory Unit of 10 Transistors with Standard 6T SRAM 33

C<SUP>2</SUP>IM: A Compact Computing-In-Memory Unit of 10 Tr...

引用

33rd IEEE International System on Chip Conference (IEEE SOCC)

作者： Ren, Erxiang Luo, Li Liu, Zheyu Wei, Qi Qiao, Fei Beijing Jiaotong Univ Dept EE Beijing Peoples R China Tsinghua Univ Dept EE BNRist Beijing Peoples R China Tsinghua Univ Dept PI ERCNT Beijing Peoples R China

ISBN: (纸本)9781728187464

memory wall has been a major bottleneck that restrains the speed and power consumption of processors in the Von Neumann architecture. computing-in-memory (CIM) was proposed as a promising method to tackle the memory wall by implementing computing in memory instead of fetching the value from memory to the processor. Based on the standard 6T-SRAM, this paper proposes a compact CIM ((CIM)-I-2) unit of 10 transistors. This (CIM)-I-2 unit is capable to not only implement the complete function of SRAM, but also realize the multiplication between the input, which is copied into the unit through the current mirror, and the value stored in the SRAM. Current-mode circuits are adopted in this unit so that it can implement higher energy efficient multiply-accumulate (MAC) operation with simpler control timing and transistor cost. Based on TSMC 65nm CMOS lower power process, the proposed unit can achieve 166.67 TOPS/W energy efficiency under 200MHz clock frequency.

关键词： computing-in-memory current-mode 6T-SRAM

来源：评论

学校读者我要写书评

暂无评论

A computing-in-memory Scheme with Series Bit-cell in STT-MRAM for Efficient Multi-bit Analog Multiplication

A Computing-in-memory Scheme with Series Bit-cell in STT-MRA...

引用

IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)

作者： Hao, Zuolei Zhang, Yue Wang, Jinkai Wang, Hongyu Bai, Yining Wang, Guanda Zhao, Weisheng Beihang Univ Fert Beijing Res Inst MIIT Key Lab Spintron Sch Integrated Circuit Sci & Engn Beijing 100191 Peoples R China Beihang Univ Hefei Innovat Res Inst Nanoelect Sci & Technol Ctr Hefei 230012 Peoples R China

ISBN: (纸本)9781665409599

computing-in-memory (CIM) is widely studied to solve the Von Neumann bottleneck, which improves energy-efficient computing. In this work, we propose a CIM with series bit-cell (SBCIM) scheme, which can perform the multi-bit analog multiplication in spin-transfer torque magnetic random access memory (STT-MRAM). Utilizing the proposed bit-cell structure consisting of three transistors and one magnetic tunnel junction (MTJ), multiple bit-cells on a column can be connected in series to overcome the inherent low on/off ratio of MTJ in CIM. Then, by converting the input data into a current injected into bit-line and the bit-line voltage into time-domain, the multiplication of two 2-bit numbers is implemented. In addition, a difference gain (DG) circuit is also designed to increase the difference of the signal representing the multiplication value, which achieves the multiplication of two 3-bit numbers. Simulation results show that the signal margin in our scheme is 10 similar to 200 times higher than that of conventional memory array in CIM schemes. Meanwhile, compared with the Spintronic Processing Unit (SPU) scheme, the delay and energy of Multiply Accumulate (MAC) operation in SBCIM scheme have been improved by 60 times and 8.8 times under 3-bit precision, respectively.

关键词： computing-in-memory Series bit-cell Multi-bit Analog multiplication STT-MRAM

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共19页 << < 2 3 4 5 6 7 8 9 10 11 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：