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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Li, Weizeng Wang, Linfang Li, Zhi Ye, Wang Zhou, Zhidao Zhou, Haiyang Gao, Hanghang Yue, Jinshan Hu, Hongyang Liu, Fengman Luo, Qing Dou, Chunmeng Chinese Acad Sci Inst Microelect Beijing Peoples R China Univ Chinese Acad Sci Beijing Peoples R China

ISBN: (纸本)9798350330991;9798350331004

In this work, we propose a two-transistor (2T) p-type channel (p-channel) logic-compatible flash cell. Compared to the previous designs, the proposed structure features reduced area-cost and enhanced ability to pass through the logic '1'. Due to these advantages, we explore its application as the reconfigurable interconnections in the chiplet-based system. By integrating them into the silicon interposer, the 2T p-channel flash cells can potentially lead to the dense and flexible interconnection between multiple computing-in-memory (CIM) chiplets, resulting in highly reconfigurable and scalable chiplet-based CIM accelerators. A 180nm 1Kb 2T p-channel flash cell array is fabricated and characterized. The characterization results show the 2T p-channel flash cells exhibit a signal ratio >10(3) over 1000 program/erase (P/E) cycles and the device-to-device variations are less than 21.07%. Their typical behaviors as routers are also confirmed by circuit simulations.

关键词： flash memory logic flash chiplet computing-in-memory reconfigurable interconnection

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DCIM-GCN: Digital computing-in-memory to Efficiently Accelerate Graph Convolutional Networks 22

DCIM-GCN: Digital Computing-in-Memory to Efficiently Acceler...

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IEEE/ACM 41st International Conference on Computer Aided-Design (ICCAD)

作者： Qiu, Yikan Ma, Yufei Zhao, Wentao Wu, Meng Ye, Le Huang, Ru Peking Univ Sch Integrated Circuits Beijing Peoples R China Peking Univ Inst Artificial Intelligence Beijing Peoples R China

ISBN: (纸本)9781450392174

computing-in-memory (CIM) is emerging as a promising architecture to accelerate graph convolutional networks (GCNs) normally bounded by redundant and irregular memory transactions. Current analog based CIM requires frequent analog and digital conversions (AD/DA) that dominate the overall area and power consumption. Furthermore, the analog non-ideality degrades the accuracy and reliability of CIM. In this work, an SRAM based digital CIM system is proposed to accelerate memory intensive GCNs, namely DCIM-GCN, which covers innovations from CIM circuit level eliminating costly AD/DA converters to architecture level addressing irregularity and sparsity of graph data. DCIM-GCN achieves 2.07x, 1.76x, and 1.89x speedup and 29.98x, 1.29x, and 3.73x energy efficiency improvement on average over CIM based PIMGCN, TARe, and PIM-GCN, respectively.

关键词： Graph Neural Networks computing-in-memory

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YOLoC: DeploY Large-Scale Neural Network by ROM-based computing-in-memory using ResiduaL Branch on a Chip 22

YOLoC: DeploY Large-Scale Neural Network by ROM-based Comput...

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59th ACM/IEEE Design Automation Conference (DAC) - From Chips to Systems - Learn Today, Create Tomorrow

作者： Chen, Yiming Yin, Guodong Tan, Zhanhong Lee, Mingyen Yang, Zekun Liu, Yongpan Yang, Huazhong Ma, Kaisheng Li, Xueqing Tsinghua Univ Elect Engn Dept BNRist ICFC Beijing Peoples R China

ISBN: (纸本)9781450391429

computing-in-memory (CiM) is a promising technique to achieve high energy efficiency in data-intensive matrix-vector multiplication (MVM) by relieving the memory bottleneck. Unfortunately, due to the limited SRAM capacity, existing SRAM-based CiM needs to reload the weights from DRAM in large-scale networks. This undesired fact weakens the energy efficiency significantly. This work, for the first time, proposes the concept, design, and optimization of computing-in-ROM to achieve much higher on-chip memory capacity, and thus less DRAM access and lower energy consumption. Furthermore, to support different computing scenarios with varying weights, a weight fine-tune technique, namely Residual Branch (ReBranch), is also proposed. ReBranch combines ROM-CiM and assisting SRAM-CiM to achieve high versatility. YOLoC, a ReBranch-assisted ROM-CiM framework for object detection is presented and evaluated. With the same area in 28nm CMOS, YOLoC for several datasets has shown significant energy efficiency improvement by 14.8x for YOLO (DarkNet-19) and 4.8x for ResNet-18, with <8% latency overhead and almost no mean average precision (mAP) loss (-0.5% similar to +0.2%), compared with the fully SRAM-based CiM.

关键词： computing-in-memory ROM-CiM Read-Only memory YOLoC

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RRAM computing-in-memory Using Transient Charge Transferring for Low-Power and Small-Latency AI Edge Inference

RRAM Computing-in-Memory Using Transient Charge Transferring...

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IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

作者： Wang, Linfang An, Junjie Ye, Wang Li, Weizeng Gao, Hanghang He, Yangu Gao, Jianfeng Yue, Jinshan Fan, Lingyan Dou, Chunmeng Chinese Acad Sci Inst Microelectron Beijing Peoples R China Univ Chinese Acad Sci Sch Microelectron Beijing Peoples R China Hangzhou Dianzi Univ Hangzhou Peoples R China

ISBN: (纸本)9781665450737

RRAM-based computing-in-memory (CIM) can potentially improve the energy- and area-efficiency for AI edge processors, yet may still suffer from performance degradations due to the large DC current and parasitic capacitance in the cell array during computation. In this work, we propose a new CIM design leveraging the transient-charge-transferring (TCT) between the parasitic capacitors in the high-density foundry-compatible two-transistor-two-resistor (2T2R) RRAM array, which can perform DC-current-free multiply-and-accumulate (MAC) operations with improved energy-efficiency, reduced latency and enhanced signal margin. The concept of TCT-CIM is silicon demonstrated using a 180nm 400Kb RRAM test-chip, which has achieved 7.36 times power reduction compared to the conventional scheme and measured read access time less than 17.22 ns.

关键词： RRAM computing-in-memory AI processor energy efficient system multiply-and-accumulate transient charge transferring and parasitic capacitance

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Exploiting and Enhancing Computation Latency Variability for High-Performance Time-Domain computing-in-memory Neural Network Accelerators 41

Exploiting and Enhancing Computation Latency Variability for...

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41st IEEE International Conference on Computer Design (ICCD)

作者： Wang, Chia-Chun Lo, Yun-Chen Wu, Jun-Shen Tsai, Yu-Chih Chang, Chia-Cheng Hsu, Tsen-Wei Chu, Min-Wei Lai, Chuan-Yao Liu, Ren-Shuo Natl Tsing Hua Univ Dept Elect Engn Hsinchu Taiwan

ISBN: (纸本)9798350342918

To address the inefficiency resulting from data movement in Von Neumann architecture, computing-in-memory (CIM) is a promising solution due to its in-situ analog computation. Among the various types of CIMs, time-domain CIM stands out as a promising solution for achieving high energy efficiency and high readout resolution by employing time-to-digital converters (TDC) instead of analog-to-digital converters (ADC) to convert time-domain delays into digital values. However, the performance of the accelerator may be constrained by the maximum operating frequency of time-domain CIM, which is significantly lower than that of digital circuits. This paper proposes an architecture for a time-domain CIM-based neural network accelerator that leverages the varying output time of the TDC. The key contributions of this work are as follows: 1) We introduce an early-termination scheme for time-domain CIM, which dynamically determines the length of the CIM clock period by deriving the maximum possible multiply-accumulate (MAC) value based on the current input. This approach reduces computation time for low-MAC results. 2) We propose an input-inversion scheme to decrease the computation time for high-MAC results. By employing linear combination, we perform bit-inversion on large inputs and compensate for the results using a low-cost digital circuit. 3) We propose a hardware optimization on the compensation circuit by combining it with shift-adders in traditional neural network accelerators. Experiments show that our schemes could gain 2x similar to 2.9x speedup under different clock period specifications with 5.82% area overhead compared to the CIM macro.

关键词： computing-in-memory Time-domain CIM Neural Network Accelerator Bit Inversion

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computing-in-memory using voltage-controlled spin-orbit torque based MRAM array

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MICROELECTRONICS JOURNAL 2021年 109卷 104943-104943页

作者： Shreya, Sonal Jain, Alkesh Kaushik, Brajesh Kumar Indian Inst Technol Roorkee Dept Elect & Commun Engn Roorkee 247667 Uttrakhand India

The computing-in-memory (CiM) is one of the best solutions to overcome the data transferring limitation between memory and processor. Moreover, spintronics based devices such as spin-transfer torque magnetic memory (STTM) and spin-orbit torque magnetic memory (SOTM) are emerging as viable contenders for CiM applications. SOTM along with their driving CMOS counterparts show a huge reduction in area and add nonvolatility to CiM designs. In this work, energy-efficient CiM working is performed using Voltage-Controlled SOTM (V-SOTM) where logic operations are implemented within the memory array. The operational conditions and working for performing logic within the memory blocks are elaborated in detail. Further, V-SOTM based full adder (FA) for CiM is presented. Performance analysis has been carried out and compared with exiting CMOS, STTM, SOTM based FA. V-SOTM FA shows 53.98% and 2.7% reduction in logic power and data transfer energy, respectively when compared to SOTM based CiM FA. Furthermore, the VCMA voltage variations for V-SOTM FA is carried out that provide performance improvement with varying voltage pulse. Finally, the effect of parametric variations is carried out using Monte Carlo analysis.

关键词： computing-in-memory Magnetic full adder MRAM SOTM STTM V-SOTM

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DE-C3: Dynamic Energy-Aware Compression for computing-in-memory-Based Convolutional Neural Network Acceleration 36

DE-C3: Dynamic Energy-Aware Compression for Computing-In-Mem...

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36th IEEE International System-on-Chip Conference (SOCC)

作者： Wu, Guan-Wei Chang, Cheng-Yang Wu, An-Yeu (Andy) Natl Taiwan Univ Dept Elect Engn Taipei Taiwan Natl Taiwan Univ Grad Inst Elect Engn Taipei Taiwan

ISBN: (纸本)9798350300116

Convolutional neural networks (CNNs) are leveraged in many applications, such as image classification and natural language processing (NLP) tasks. However, the hardware implementation of CNNs not only occupies a considerable amount of memory space but also incurs high computational demands, which can lead to significant energy cost for data transfer. Therefore, an emerging computing-in-memory (CIM)-based architecture has been proposed to alleviate the energy bottleneck of CNNs. Various model compression methods have recently been studied to enhance energy efficiency of the CIM-based accelerator, including quantization and pruning. However, these works are separately discussed with the static inference scenario. In this paper, the proposed DE-C3 can dynamically and jointly design the compression strategy. Besides, it adopts trainable energy-aware thresholds for both quantization and pruning scenarios. Experimental results based on the CIFAR-10 dataset show that our DE-C3 achieves up to 3.4x the energy reduction compared to state-of-the-art works.

关键词： Convolutional neural network computing-in-memory energy-aware training dynamic inference

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C²IM: A Compact computing-in-memory Unit of 10 Transistors with Standard 6T SRAM 33

C<SUP>2</SUP>IM: A Compact Computing-In-Memory Unit of 10 Tr...

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33rd IEEE International System on Chip Conference (IEEE SOCC)

作者： Ren, Erxiang Luo, Li Liu, Zheyu Wei, Qi Qiao, Fei Beijing Jiaotong Univ Dept EE Beijing Peoples R China Tsinghua Univ Dept EE BNRist Beijing Peoples R China Tsinghua Univ Dept PI ERCNT Beijing Peoples R China

ISBN: (纸本)9781728187464

memory wall has been a major bottleneck that restrains the speed and power consumption of processors in the Von Neumann architecture. computing-in-memory (CIM) was proposed as a promising method to tackle the memory wall by implementing computing in memory instead of fetching the value from memory to the processor. Based on the standard 6T-SRAM, this paper proposes a compact CIM ((CIM)-I-2) unit of 10 transistors. This (CIM)-I-2 unit is capable to not only implement the complete function of SRAM, but also realize the multiplication between the input, which is copied into the unit through the current mirror, and the value stored in the SRAM. Current-mode circuits are adopted in this unit so that it can implement higher energy efficient multiply-accumulate (MAC) operation with simpler control timing and transistor cost. Based on TSMC 65nm CMOS lower power process, the proposed unit can achieve 166.67 TOPS/W energy efficiency under 200MHz clock frequency.

关键词： computing-in-memory current-mode 6T-SRAM

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H-RIS: Hybrid computing-in-memory Architecture Exploring Repetitive Input Sharing 56

H-RIS: Hybrid Computing-in-Memory Architecture Exploring Rep...

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56th IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Chen, Yu-Chen Chang, Cheng-Yang Wu, An-Yeu (Andy) Natl Taiwan Univ Dept Elect Engn Taipei Taiwan Natl Taiwan Univ Grad Inst Elect Engn Taipei Taiwan

ISBN: (纸本)9781665451093

computing-in-memory (CIM) has become a potential trend for accelerating convolutional neural networks (CNNs). Ongoing research, e.g., Repetitive Input Sharing (RIS), focuses on removing redundant matrix-vector multiplication (MVM) by exploiting computational reuse for higher energy efficiency. However, we argue that the RIS neglects the extra overheads of the computation reuse scheme. Moreover, analog CIM is inherently vulnerable to noise. Consequently, reusing the noisy MVM results may lead to severe accuracy degradation. To address the above issues, we first evaluate the extra buffer overheads resulting from the computation reuse scheme for storing repetitive MVM results in the buffer. Based on our evaluation, we find an optimal RIS reuse ratio that balances between buffer costs and the efficiency gain from computation reuse, leading to more energy reduction. In addition, we introduce the RIS-based Hybrid-CIM (H-RIS), which mixes up the analog CIM and digital near-memory-computing (NMC) at the pattern level to maintain accuracy. Based on the above techniques, when we set the RIS ratio to 25%, H-RIS increases 18% accuracy compared with the pure analog CIM and also reduces 97% energy compared with the pure digital NMC.

关键词： computing-in-memory activation compression hybrid-CIM deep neural networks (DNNs)

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A 2.53μW/channel Event-Driven Neural Spike Sorting Processor with Sparsity-Aware computing-in-memory Macros 56

A 2.53μW/channel Event-Driven Neural Spike Sorting Processo...

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56th IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Jiang, Hao Zheng, Jiapei Wang, Yunzhengmao Zhang, Jinshan Zhu, Haozhe Lyu, Liangjian Chen, Yingping Chen, Chixiao Liu, Qi Fudan Univ Frontier Inst Chip & Syst State Key Lab Integrated Chips & Syst Shanghai Peoples R China East China Normal Univ Sch Commun & Elect Engn Shanghai Peoples R China

ISBN: (纸本)9781665451093

Spike sorting processors with high energy efficiency are widely used in large-scale neural signal processing tasks to monitor the activity of neurons in brains. This paper presents a low-power processor for high-accuracy spike sorting and onchip incremental learning using an algorithm-hardware co-design approach. The processor introduces an event-driven mechanism with adaptive-threshold detection to conditionally activate the system in order to reduce power consumption. Sparsity-aware computing-in-memory (CIM) macros are also developed in our design to store templates and perform complicated computations efficiently. The prototype is designed using 28nm technology with an area of 0.018 mm(2)/channel and an overall power efficiency of 2.53 mu W/channel and 84nW/(channel center dot cluster) at the voltage of 0.72V. Moreover, the accuracy of the whole design can reach 94.5% in a 32-channel scenario.

关键词： spike sorting template matching on-chip learning event-driven adaptive threshold computing-in-memory sparsity low power

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