检索结果-内蒙古大学图书馆

Near-threshold-voltage operation in flash-based high-precision computing-in-memory to implement Poisson image editing

引用

Science China(Information Sciences) 2023年第12期66卷 261-266页

作者： Yang FENG Bing CHEN Mingfeng TANG Yueran QI Maoying BAI Chengcheng WANG Hai WANG Xuepeng ZHAN Junyu ZHANG Jing LIU Jixuan WU Jiezhi CHEN School of Information Science and Engineering Shandong University School of Micro-nano Electronics Zhejiang University Neumem Co. Ltd Key Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics of Chinese Academy of Sciences

We propose a NOR flash-based computing-in-memory(CIM) to implement high-precision(32-bit) Poisson image editing, including the gradient operations and Laplace operation. To meet the requirements of image processing, CIM operation schemes and reliabilities are carefully studied and optimized,showing that the power consumption at the near-threshold-voltage(NTV) region can be as low as 40 fJ/bit,which is two orders lower than working at the saturation region. High-temperature retention, as well as various disturbs, are also analyzed. The proposed CIM scheme can be applied as an energy-efficient approach to construct the high-precision image processing accelerator.

关键词： NOR flash memory computing-in-memory variation Poisson image editing

来源：评论

学校读者我要写书评

暂无评论

Array-level boosting method with spatial extended allocation to improve the accuracy of memristor based computing-in-memory chips

引用

Science China(Information Sciences) 2021年第6期64卷 80-88页

作者： Wenqiang ZHANG Bin GAO Peng YAO Jianshi TANG He QIAN Huaqiang WU Institute of Microelectronics Beijing National Research Center for Information Science and Technology (BNRist)Tsinghua University Institute of Microelectronics Beijing National Research Center for Information Science and Technology (BNRist)Tsinghua University

Memristor based computing-in-memory chips have shown the potentials to accelerate deep neural networks with high energy efficiency. Due to the inherent filament-based conductive mechanism of the memristor, the reading and writing noises are hard to eliminate. Besides, the precision of the large-scale memristor array is still limited. However, when the noise of the memristor is large, the existing training methods to reduce the accuracy loss of memristor based computing-in-memory chips will face ***, we proposed the array-level boosting method with spatial extended allocation to reduce the accuracy loss induced by the limited precision and large noises. To optimize the spatial allocation number of each layer in the neural network, the greedy spatial extended allocation algorithm is also proposed. The image processing and classification tasks are demonstrated based on fabricated 32×128 memristor arrays to valid the performance of the proposed method. The chip-in-loop results show that the recovered accuracy of ResNet-34 on CIFAR-10 with array-level boosting method is 92.3%, which is closed to software-based accuracy of 93.2%.

关键词： memristor computing-in-memory array-level boosting neuromorphic computing RRAM

来源：评论

学校读者我要写书评

暂无评论

Spiking Neural Network with Memristive Based computing-in-memory Circuits and Architecture

Spiking Neural Network with Memristive Based Computing-In-Me...

引用

作者： Nowshin, Fabiha Virginia Tech | University

In recent years neuromorphic computing systems have achieved a lot of success due to its ability to process data much faster and using much less power compared to traditional Von Neumann computing architectures. There are two main types of Artificial Neural Networks (ANNs), Feedforward Neural Network (FNN) and Recurrent Neural Network (RNN). In this thesis we first study the types of RNNs and then move on to Spiking Neural Networks (SNNs). SNNs are an improved version of ANNs that mimic biological neurons closely through the emission of spikes. This shows significant advantages in terms of power and energy when carrying out data intensive applications by allowing spatio-temporal information processing. On the other hand, emerging non-volatile memory (eNVM) technology is key to emulate neurons and synapses for in-memory computations for neuromorphic hardware. A particular eNVM technology, memristors, have received wide attention due to their scalability, compatibility with CMOS technology and low power consumption properties. In this work we develop a spiking neural network by incorporating an inter-spike interval encoding scheme to convert the incoming input signal to spikes and use a memristive crossbar to carry out in-memory computing operations. We develop a novel input and output processing engine for our network and demonstrate the spatio-temporal information processing capability. We demonstrate an accuracy of a 100% with our design through a small-scale hardware simulation for digit recognition and demonstrate an accuracy of 87% in software through MNIST simulations.

关键词： Neuromorphic computing Spiking Neural Network Reservoir computing Pattern Recognition Digit Recognition Memristor computing-in-memory LIF Neuron Thesis

来源：评论

学校读者我要写书评

暂无评论

Trends and Challenges in computing-in-memory for Neural Network Model: A Review From Device Design to Application-Side Optimization

引用

IEEE ACCESS 2024年 12卷 186679-186702页

作者： Yu, Ke Kim, Sunmean Choi, Jun Rim Kyungpook Natl Univ Sch Elect & Elect Engn Daegu 41566 South Korea Kyungpook Natl Univ Sch Elect Engn Coll IT Engn Daegu 41566 South Korea

Neural network models have been widely used in various fields as the main way to solve problems in the current artificial intelligence (AI) field. Efficient execution of neural network models requires devices with massively parallel Multiply-accumulate (MAC) and Matrix-vector Multiplication (MVM) computing capability. However, existing computing devices based on von Neumann architecture suffer from bottlenecks, and the separation of memory and computation module makes data on the move wasting a lot of meaningless computation time and energy. computing-in-memory (CIM) based on performing MAC computation inside the memory is considered a promising direction to solve this problem. However, large-scale application of CIM still faces challenges due to the non-idealities of current CIM devices and the lack of a common and reliable programmable interface on the application side. In this paper, we will comprehensively analyze the current problems faced by CIMs from various perspectives, such as CIM memory arrays, peripheral circuits, and application-side design, and discuss the possible future development opportunities of CIMs.

关键词： Computational modeling Random access memory Common Information Model (computing) Computer architecture Biological neural networks Artificial intelligence In-memory computing Performance evaluation Arrays Voltage Neural network model von Neumann architecture computing-in-memory multiply-accumulate matrix-vector multiplication peripheral circuits memory array

来源：评论

学校读者我要写书评

暂无评论

An Ultra-Low-Power Analog Multiplier-Divider Compatible with Digital Code for RRAM-Based computing-in-memory Macros

引用

MICROMACHINES 2023年第7期14卷 1482-1482页

作者： Yang, Yiming Lv, Shidong Li, Xiaoran Wang, Xinghua Wang, Qian Yuan, Yiyang Liang, Sen Zhang, Feng Beijing Inst Technol Sch Integrated Circuits & Elect Beijing 100081 Peoples R China BIT Chongqing Inst Microelect & Microsyst Chongqing 401332 Peoples R China Beijing Inst Technol Yangtze Delta Reg Acad Jiaxing 314000 Peoples R China Chinese Acad Sci Inst Microelect Beijing 100029 Peoples R China

This manuscript presents an ultra-low-power analog multiplier-divider compatible with digital code words, which is applicable to the integrated structure of resistive random-access memory (RRAM)-based computing-in-memory (CIM) macros. Current multiplication and division are accomplished by a current-mirror-based structure. Compared with digital dividers to achieve higher precision and operation speed, analog dividers present the advantages of a reduced power consumption and a simple circuit structure in lower precision operations, thus improving the energy efficiency. Designed and fabricated in a 55 nm CMOS process, the proposed work is capable of achieving 8-bit precision for analog current multiplication and division operations. Measurement results show that the signal delay is 1 & mu;s when performing 8-bit operation, with a bandwidth of 1.4 MHz. The power consumption is less than 6.15 & mu;W with a 1.2 V supply voltage. The proposed multiplier-divider can increase the operation capacity by dividing the input current and digital code while reducing the power consumption and complexity required by division, which can be further utilized in real-time operation of edge computing devices.

关键词： CMOS computing-in-memory current mirror edge computing multiplier-divider

来源：评论

学校读者我要写书评

暂无评论

Capacitance and Conductance Compensation Methods for Efficient computing-in-memory Designs

引用

ADVANCED ELECTRONIC MATERIALS 2024年第12期10卷

作者： Luo, Yubiao Qiao, Fei Sun, Zhong Peking Univ Sch Integrated Circuits Beijing 100871 Peoples R China Peking Univ Inst Artificial Intelligence Beijing 100871 Peoples R China Tsinghua Univ Dept Elect Engn Sense Lab Beijing 100084 Peoples R China Beijing Adv Innovat Ctr Integrated Circuits Beijing 100871 Peoples R China

Compensation has been a common while unacknowledged strategy in the design of computing-in-memory (CIM) schemes. It enables efficient CIM designs by intentionally letting the sum of capacitances or conductances of two or more rows or columns in the memory array equal, thus resulting in a concise mathematical formula regarding the memory cell data and the input data, which constitute computing primitives. Here, the capacitance and conductance compensation methods are reviewed that have been used for CIM designs based on static random-access memory (SRAM) in combination with capacitors and nonvolatile resistive memory, respectively, and uncover the underlying principles and their application to CIM. It is hoped this effort will help recognize the compensation methods as a building block for CIM designs, and will be an inspiration to developing more CIM schemes that are more compact in area, more efficient in energy consumption, and capable of solving more complicated problems. This review concludes the capacitance compensation (CapCom) and conductance compensation (ConCom) methods for static random-access memory-based and resistive memory-based computing-in-memory (CIM) schemes, respectively. In pairwise CIM schemes, CapCom and ConCom enable load balancing between two differential input ports, while in the entire CIM scheme, they render the load of all bit-line (or source-line) equal, thus reaching more compact CIM schemes. image

关键词： capacitance compensation computing-in-memory conductance compensation resistive memory SRAM

来源：评论

学校读者我要写书评

暂无评论

Extreme Partial-Sum Quantization for Analog computing-in-memory Neural Network Accelerators

引用

ACM JOURNAL ON EMERGING TECHNOLOGIES IN computing SYSTEMS 2022年第4期18卷 75-75页

作者： Kim, Yulhwa Kim, Hyungjun Kim, Jae-Joon Pohang Univ Sci & Technol 77 Cheongam Ro Pohang 37673 Gyeongsangbuk D South Korea Seoul Natl Univ 1 Gwanak Ro Seoul 08826 South Korea

In Analog computing-in-memory (CIM) neural network accelerators, analog-to-digital converters (ADCs) are required to convert the analog partial sums generated from a CIM array to digital values. The overhead from ADCs substantially degrades the energy efficiency of CIM accelerators so that previous works attempted to lower the ADC resolution considering the distribution of the partial sums. Despite the efforts, the required ADC resolution still remains relatively high. In this article, we propose the data-driven partial sum quantization scheme, which exhaustively searches for the optimal quantization range with little computational burden. We also report that analyzing the characteristics of the partial sum distributions at each layer gives an additional information to further reduce the ADC resolution compared to previous works that mostly used the characteristics of the partial sum distributions of the entire network. Based on the finer-level data-driven approach combined with retraining, we present a methodology for extreme partial-sum quantization. Experimental results show that the proposed method can reduce the ADC resolution to 2 to 3 bits for CIFAR-10 dataset, which is the smaller ADC bit resolution than any previous CIM-based NN accelerators.

关键词： computing-in-memory processing-in-memory neural networks analog computing

来源：评论

学校读者我要写书评

暂无评论

A hybrid precision low power computing-in-memory architecture for neural networks

引用

MICROPROCESSORS AND MICROSYSTEMS 2021年 80卷 103351-103351页

作者： Xu, Rui Tao, Linfeng Wang, Tianqi Jin, Xi Li, Chenxia Li, Zhengda Ren, Jun Univ Sci & Technol China Key Lab Strongly Coupled Quantum Matter Phys Chinese Acad Sci Sch Phys Sci Hefei Anhui Peoples R China Zbit Semicond Inc Hefei Anhui Peoples R China

Recently, non-volatile memory-based computing-in-memory has been regarded as a promising competitor to ultra-low-power AI chips. Implementations based on both binarized (BIN) and multi-bit (MB) schemes are proposed for DNNs/CNNs. However, there are challenges in accuracy and power efficiency in the practical use of both schemes. This paper proposes a hybrid precision architecture and circuit-level techniques to overcome these challenges. According to measured experimental results, a test chip based on the proposed architecture achieves (1) from binarized weights and inputs up to 8-bit input, 5-bit weight, and 7-bit output, (2) an accuracy loss reduction of from 86% to 96% for multiple complex CNNs, and (3) a power efficiency of 2.15TOPS/W based on a 0.22 mu m CMOS process which greatly reduces costs compared to digital designs with similar power efficiency. With a more advanced process, the architecture can achieve a higher power efficiency. According to our estimation, a power efficiency of over 20TOPS/W can be achieved with a 55nm CMOS process.

关键词： Neuromorphic computing computing-in-memory Non-volatile memory

来源：评论

学校读者我要写书评

暂无评论

Hafnium Oxide-Based Ferroelectric Devices for computing-in-memory Applications

引用

PHYSICA STATUS SOLIDI A-APPLICATIONS AND MATERIALS SCIENCE 2021年第9期218卷 2000635-2000635页

作者： Chen, Pei-Yao He, Zheng-Yu Cha, Ming-Yang Liu, Hao Zhu, Hao Chen, Lin Sun, Qing-Qing Ding, Shi-Jin Zhang, David Wei Fudan Univ Sch Microelect State Key Lab ASIC & Syst Shanghai 200433 Peoples R China

Herein, a layer of 10 nm ferroelectric Al-doped HfO2 (HAO) film is fabricated and optimized and is further integrated in a nonvolatile memory device with TiN/HAO/Pt/Ti capacitor structure. Long retention, high endurance, and stable storage characteristics, as well as a competitive residual polarization of 2Pr = 24-30 mu C cm(-2) are achieved. Furthermore, computing-in-memory applications are implemented utilizing the HAO-based ferroelectric memory devices. Typical NOR and NOT logic gates are obtained based on the memristor-aided logic (MAGIC) operations by exploiting the polarization inversion characteristics of the device, which show great potential in realizing other basic Boolean logic operations. The results show that the HAO-based ferroelectric memory device is a strong candidate in the pursuit of next-generation parallel storage and computing systems.

关键词： aluminum-doped HfO2 computing-in-memory ferroelectric nonvolatile

来源：评论

学校读者我要写书评

暂无评论

Monolithic 3D Integration of Analog RRAM-Based computing-in-memory and Sensor for Energy-Efficient Near-Sensor computing

引用

ADVANCED MATERIALS 2024年第22期36卷 2302658-2302658页

作者： Du, Yiwei Tang, Jianshi Li, Yijun Xi, Yue Li, Yuankun Li, Jiaming Huang, Heyi Qin, Qi Zhang, Qingtian Gao, Bin Deng, Ning Qian, He Wu, Huaqiang Tsinghua Univ Beijing Adv Innovat Ctr Integrated Circuits Beijing Natl Res Ctr Informat Sci & Technol BNRist Sch Integrated Circuits Beijing 100084 Peoples R China

In the era of the Internet of Things, vast amounts of data generated at sensory nodes impose critical challenges on the data-transfer bandwidth and energy efficiency of computing hardware. A near-sensor computing (NSC) architecture places the processing units closer to the sensors such that the generated data can be processed almost in situ with high efficiency. This study demonstrates the monolithic three-dimensional (M3D) integration of a photosensor array, analog computing-in-memory (CIM), and Si complementary metal-oxide-semiconductor (CMOS) logic circuits, named M3D-SAIL. This approach exploits the high-bandwidth on-chip data transfer and massively parallel CIM cores to realize an energy-efficient NSC architecture. The 1st layer of the Si CMOS circuits serves as the control logic and peripheral circuits. The 2nd layer comprises a 1 k-bit one-transistor-one-resistor (1T1R) array with InGaZnOx field-effect transistor (IGZO-FET) and resistive random-access memory (RRAM) for analog CIM. The 3rd layer comprises multiple IGZO-FET-based photosensor arrays for wavelength-dependent optical sensing. The structural integrity and function of each layer are comprehensively verified. Furthermore, NSC is implemented using the M3D-SAIL architecture for a typical video keyframe-extraction task, achieving a high classification accuracy of 96.7% as well as a 31.5x lower energy consumption and 1.91x faster computing speed compared to its 2D counterpart.

关键词： computing-in-memory InGaZnOx field-effect transistor monolithic 3D integration near-sensor computing resistive random-access memory

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：