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Generic Parity-Based concurrent error detection for Lightweight ARX Ciphers

IEEE ACCESS 2020年 8卷 142016-142025页

作者： Bauer, Sergei Rass, Stefan Schartner, Peter Kompetenzzentrum Automobil & Ind Elekt KAI GmbH A-9524 Villach Austria Univ Klagenfurt Syst Secur Res Grp A-9020 Klagenfurt Austria

Cryptographic functions for constrained processing environments can be devised using lightweight cryptography. For use in safety relevant automotive applications where transient faults can occur at runtime the calculation of a cipher text requires verification. We propose an algorithm to generate a group parity based concurrent error detection for generic ciphers based on addition, rotation and XOR (ARX). The generated function is capable of detecting odd hamming weight faults according to the single event error model used in automotive applications. The the generated fault detection scheme is smaller in circuit size than presently existing concurrent error detection schemes and can be executed parallel to the cryptographic function. We provide a proof for the correctness of the generated prediction function and estimate the circuit complexity in terms of size and depth. We evaluate our solution in terms of gate count and throughput on IC synthesis level.

关键词： Ciphers Circuit faults Transient analysis Fault detection Logic gates Integrated circuits concurrent error detection group based parity prediction lightweight cryptography ARX cipher primitive directed acyclic graph transient fault

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An Implication-based Test Scheme for Both Diagnosis and concurrent error detection Applications

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ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 2020年第1期25卷 3-3页

作者： Wang, Chih-Hao Hsieh, Tong-Yu Natl Sun Yat Sen Univ Kaohsiung Taiwan 70 Lienhai Rd Kaohsiung 80424 Taiwan

This article describes a diagnosis-aware hybrid concurrent error detection (DAH-CED) scheme that can facilitate both off-line and on-line test applications. By using the proposed scheme, not only the probability of detecting errors (on-line) but also the diagnosability of the target circuit (off-line) can be significantly enhanced. The proposed scheme combines the implication-based method with the parity check method. In particular, novel algorithms are developed to identify specific implications for enhancing the diagnosability for the modeled faults proactively. Furthermore, a reduction algorithm is also presented to minimize the number of the employed implications, while no loss on probability of detecting errors and diagnosability is also guaranteed. To the best of our knowledge, this issue is not addressed in the literature. To validate the proposed scheme, not only stuck-at faults but also transition faults are considered to simulate the timing-related errors. The experimental results on nine ITC'99 benchmark circuits show that the diagnosability for stuck-at (transition) faults is enhanced by 6.88% (7.78%) by applying the proposed scheme. As for the probability of detecting errors, 97.73% (97.10%) is achieved for errors caused by stuck-at (transition) faults. Moreover, only 3.11% of implications are needed.

关键词： Implication concurrent error detection fault diagnosis

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A Delay-Aware Implementation Scheme for Cost-Effective Implication-Based concurrent error detection 3

A Delay-Aware Implementation Scheme for Cost-Effective Impli...

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IEEE International Test Conference in Asia (ITC-Asia)

作者： Hsieh, Tong-Yu Lin, Kuang-Chun Lin, Hsin-Hsien Natl Sun Yat Sen Univ Dept Elect Engn Kaohsiung Taiwan

ISBN: (纸本)9781728147185

Implications have been shown to be beneficial for both concurrent error detection and diagnosis. To reduce the incurred hardware cost, one critical issue is selection of a minimum number of appropriate implications. Although the previous work developed several implication selection algorithms, the critical path delay may still be high. This is because the factors related to the critical path delay have not been well studied and considered during implication selection. In this paper, we investigate these factors and develop a new delay-aware implication selection algorithm. A buffer insertion algorithm is also developed such that the minimum number of buffers are inserted to further reduce the delay. This algorithm is integrated with the implication selection algorithm as a delay-aware implementation scheme. Experimental results on 18 ISCAS'85 and ITC'99 benchmark circuits show that 29.02% delay overhead reduction is achieved on average with only additional 0.34% implications selected.

关键词： concurrent error detection delay overhead implications implication reduction probability of error detection

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A Comparison of Dual Modular Redundancy and concurrent error detection in Finite Impulse Response Filters Implemented in SRAM-Based FPGAs Through Fault Injection

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2018年第3期65卷 376-380页

作者： Alberto Aranda, Luis Reviriego, Pedro Antonio Maestro, Juan Univ Antonio Nebrija ARIES Res Ctr Madrid 28040 Spain

Compared with application specific integrated circuits (ASICs), static random access memory (SRAM)-based field programmable gate arrays (FPGAs) respond differently to radiation due to the configuration memory vulnerability. In this brief, the differences between the permanent error model for SRAM-based FPGAs due to configuration memory single event upsets (SEUs), and the ASIC SEU error model are put into perspective for error detection schemes. In particular, a concurrent error detection (CED) technique for finite impulse response filters in ASICs is implemented and evaluated in an SRAM-based FPGA through fault injection emulation. This method is compared with a dual modular redundancy (DMR) scheme in order to obtain a common behavior. The analysis of experimental data indicates that the CED technique has less undetected errors than DMR. However, our exhaustive fault injection tests reveal that false positive detections are more likely to occur in CED, since the error detection branch uses more FPGA resources than the DMR comparator. This phenomenon, which is negligible in ASICs, implies a partial or complete unnecessary reconfiguration, so it should be considered in SRAM-based FPGAs.

关键词： Dual modular redundancy concurrent error detection SRAM-based FPGA finite impulse response filter fault injection

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error Indication Signal Collapsing for Implication-Based concurrent error detection 2

Error Indication Signal Collapsing for Implication-Based Con...

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2nd IEEE International Test Conference in Asia (ITC-Asia)

作者： Wang, Chih-Hao Ho, Chi-Hsuan Hsieh, Tong-Yu Natl Sun Yat Sen Univ Dept Elect Engn Kaohsiung Taiwan

ISBN: (纸本)9781538651803

Implication-based concurrent error detection (CED) has been shown to have promising performance for online testing. However, many error indication signals may be required for this CED method, and thus incur much additional interconnection. This would result in not only complicated error checking circuits, but also a large compactor design to process the error indication signals. Both would incur high area overhead. In this paper, we present a collapsing technique that can significantly reduce the total number of required error indication signals for implications. This issue has never been addressed in the literature. We find that equivalence and dominance relationships exist between error indication signals, which are quite helpful for signal reduction. Therefore we develop an efficient algorithm to first identify these relationships, and then make good use of them to merge error indication signals without sacrificing the probability of detecting errors. We also employ 19 ISCAS'85 and ITC'99 benchmark circuits to evaluate the effectiveness of the proposed technique. The results show that 48.48% of error indication signals are reduced by our technique on average. This also leads to 39.23% and 34.52% averaged area overhead reduction to the error checking circuit and the compactor design, respectively.

关键词： concurrent error detection dominance equivalence implications signal collapsing

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Floating-Point Multiplier with concurrent error detection Capability by Partial Duplication

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IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 2017年第3期E100D卷 531-536页

作者： Kito, Nobutaka Akimoto, Kazushi Takagi, Naofumi Chukyo Univ Sch Engn Toyota 4700393 Japan Kyoto Univ Grad Sch Informat Kyoto 6068501 Japan

A floating-point multiplier with concurrent error detection capability by partial duplication is proposed. It uses a truncated multiplier for checking of the significand (mantissa) multiplication instead of full duplication. The proposed multiplier can detect any erroneous output with error larger than one unit in the last place (1 ulp) of the significand, which may be overlooked by residue checking. Its circuit area is smaller than that of a fully duplicated one. Area overhead of a single-precision multiplier is about 78% and that of a double-precision one is about 65%.

关键词： concurrent error detection floating-point multiplier duplication truncated multiplier

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Sum Codes with Efficient detection of Twofold errors for Organization of concurrent error-detection Systems of Logical Devices

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AUTOMATION AND REMOTE CONTROL 2018年第4期79卷 665-678页

作者： Dmitriev, V. V. Efanov, D. V. Sapozhnikov, V. V. Sapozhnikov, Vl. V. Emperor Alexander 1St Petersburg State Transport St Petersburg Russia

Developed were new sum codes detecting efficiently twofold errors in the data vectors. A method of constructing concurrent error-detection systems of the logical combination devices with detection of all single malfunctions based on decomposing the outputs into individual groups and checking them with the use of new sum codes was proposed.

关键词： concurrent error detection combinational device sum code Berger code data vector properties of error detection

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Security analysis of concurrent error detection against differential fault analysis

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JOURNAL OF CRYPTOGRAPHIC ENGINEERING 2015年第3期5卷 153-169页

作者： Guo, Xiaofei Mukhopadhyay, Debdeep Jin, Chenglu Karri, Ramesh NYU Sch Engn ECE Dept Brooklyn NY 11201 USA Indian Inst Technol Kharagpur Dept Comp Sci & Engn Kharagpur W Bengal India

Differential fault analysis (DFA) poses a significant threat to advanced encryption standard (AES). Only a single faulty ciphertext is required to extract the secret key. concurrent error detection (CED) is widely used to protect AES against DFA. Traditionally, these CEDs are evaluated with uniformly distributed faults, the resulting fault coverage indicates the security of CEDs against DFA. However, DFA-exploitable faults, which are a small subspace of the entire fault space, are not uniformly distributed. Therefore, fault coverage does not accurately measure the security of the CEDs against DFA. We provide a systematic study of DFA of AES and show that an attacker can inject biased faults to improve the success rate of the attacks. We propose fault entropy (FE) and fault differential entropy (FDE) to evaluate CEDs. We show that most CEDs with high fault coverage are not secure when evaluated with FE and FDE. This work challenges the traditional use of fault coverage for uniformly distributed faults as a metric for evaluating the security of CEDs against DFA.

关键词： Fault attack Differential fault analysis concurrent error detection Advanced encryption standard Block cipher

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Low-Cost concurrent error detection for GCM and CCM

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JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS 2014年第6期30卷 725-737页

作者： Guo, Xiaofei Karri, Ramesh NYU ECE Dept Brooklyn NY 11201 USA

In many applications, encryption alone does not provide enough security. To enhance security, dedicated authenticated encryption (AE) mode are invented. Galios Counter Mode (GCM) and Counter with CBC-MAC mode (CCM) are the AE modes recommended by the National Institute of Standards and Technology. To support high data rates, AE modes are usually implemented in hardware. However, natural faults reduce its reliability and may undermine both its encryption and authentication capability. We present a low-cost concurrent error detection (CED) scheme for 7 AE architectures. The proposed technique explores idle cycles of the AE mode architectures. Experimental results shows that the performance overhead can be lower than 100 % for all architectures depending on the workload. FPGA implementation results show that the hardware overhead in the 0.1-23.3 % range and the power overhead is in the 0.2-23.2 % range. ASIC implementation results show that the hardware overhead in the 0.1-22.8 % range and the power overhead is in the 0.3-12.6 % range. The underlying block cipher and hash module need not have CED built in. Thus, it allows system designers to integrate block cipher and hash function intellectual property from different vendors.

关键词： concurrent error detection Reliability Authenticated encryption modes GCM CCM

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A High Radix Montgomery Multiplier with concurrent error detection 9

A High Radix Montgomery Multiplier with Concurrent Error Det...

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9th International Design & Test Symposium (IDT)

作者： Zervakis, Georgios Eftaxiopoulos, Nikolaos Tsoumanis, Kostas Axelos, Nicholas Pekmestzi, Kiamal Natl Tech Univ Athens Sch Elect & Comp Engn Dept Comp Sci Athens Greece

ISBN: (纸本)9781479982004

Modular multiplication is essential in cryptographic algorithms (e.g. RSA), as it determines the performance of the entire cryptographic operation and its reliability is crucial for the system security. In this paper, we propose a high-radix Montgomery Modular Multiplication (MMM) implementation and conduct an exploration to find the optimal radix. Also, a concurrent error detection circuit with 99.9% detection rate, small area and power overheads (2.24% and 1.46% respectively) is proposed to protect the MMM against fault attacks and natural faults.

关键词： Montgomery modular multiplication concurrent error detection fault attack high-radix RSA

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