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Efficient Profiling of Actor-based Applications in Parallel and Distributed Systems 11

Efficient Profiling of Actor-based Applications in Parallel ...

11th Workshop on Implementation, Compilation, Optimization of Object-Oriented Languages, Programs and Systems (ICOOOLPS)

作者： Rosa, Andrea Chen, Lydia Y. Binder, Walter Univ Svizzera Italiana Fac Informat Lugano Switzerland IBM Res Lab Zurich Cloud Server Technol Grp Ruschlikon Switzerland

ISBN: (纸本)9781450348379

Applications employing the actor model of concurrent computation are becoming popular nowadays. On the one hand, the foundational characteristics of the actor model make it attractive in parallel and distributed settings. On the other hand, effective investigation of poor performance in actor based applications requires dedicated metrics and profiling methods. Unfortunately, little research has been conducted on this topic to date, and developers are forced to investigate suboptimal performance with general-purpose profilers that fall short in locating scalability bottlenecks and performance inefficiencies. This position paper advocates the need for dedicated profiling techniques and tools for actor-based applications, focusing specifically on inter-actor communication and actor utilization. Our preliminary results support the importance of dedicated actor profiling and motivate further research on this topic.

关键词： Actor model concurrent programming profiling optimization parallel and distributed systems

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Experiences of Applying One-Sided Communication to Nearest-Neighbor Communication 1

Experiences of Applying One-Sided Communication to Nearest-N...

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1st PGAS Applications Workshop (PAW)

作者： Shan, Hongzhang Williams, Samuel Zheng, Yili Zhang, Weiqun Wang, Bei Ethier, Stephane Zhao, Zhengji Lawrence Berkeley Natl Lab Computat Res Div Berkeley CA 94720 USA Princeton Univ PICSciE Princeton NJ 08540 USA Princeton Univ Princeton Plasma Phys Lab Princeton NJ 08540 USA Lawrence Berkeley Natl Lab NERSC Berkeley CA 94720 USA

ISBN: (纸本)9781509052141

Nearest-neighbor communication is one of the most important communication patterns appearing in many scientific applications. In this paper, we discuss the results of applying UPC++, a library-based partitioned global address space (PGAS) programming extension to C++, to an adaptive mesh framework (BoxLib), and a full scientific application GTC-P, whose communications are dominated by the nearest-neighbor communication. The results on a Cray XC40 system show that compared with the highly-tuned MPI two-sided implementations, UPC++ improves the communication performance up to 60% and 90% for BoxLib and GTC-P, respectively. We also implement the nearest-neighbor communication using MPI one-sided messages. The performance comparison demonstrates that the MPI one-sided implementation can also improve the communication performance over the two-sided version but not so significantly as UPC++ does.

关键词： concurrent programming Performance measures

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Reactive Async: Expressive Deterministic Concurrency 7

Reactive Async: Expressive Deterministic Concurrency

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7th ACM SIGPLAN Symposium on Scala

作者： Haller, Philipp Geries, Simon Eichberg, Michael Salvaneschi, Guido KTH Royal Inst Technol Stockholm Sweden Tech Univ Darmstadt Darmstadt Germany

ISBN: (纸本)9781450346481

concurrent programming is infamous for its difficulty. An important source of difficulty is non-determinism, stemming from unpredictable interleavings of concurrent activities. Futures and promises are widely-used abstractions that help designing deterministic concurrent programs, although this property cannot be guaranteed statically in mainstream programming languages. Deterministic-by-construction concurrent programming models avoid this issue, but they typically restrict expressiveness in important ways. This paper introduces a concurrent programming model, Reactive Async, which decouples concurrent computations using so-called cells, shared locations which generalize futures as well as recent deterministic abstractions such as LVars. Compared to previously proposed programming models Reactive Async provides (a) a fallback mechanism for the case where no computation ever computes the value of a given cell, and (b) explicit and optimized handling of cyclic dependencies. We present a complete implementation of the Reactive Async programming model as a library in Scala. Finally, the paper reports on a case study applying Reactive Async to static analyses of JVM bytecode based on the Opal framework.

关键词： asynchronous programming concurrent programming deterministic concurrency static analysis Scala

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The Future(s) of Transactional Memory 45

The Future(s) of Transactional Memory

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45th International Conference on Parallel Processing (ICPP)

作者： Zeng, Jingna Barreto, Joao Haridi, Seif Rodrigues, Luis Romano, Paolo KTH Royal Inst Technol Stockholm Sweden Univ Lisbon INESC ID Inst Super Tecn P-1699 Lisbon Portugal

ISBN: (纸本)9781509028238

This work investigates how to combine two powerful abstractions to manage concurrent programming: Transactional Memory (TM) and futures. The former hides from programmers the complexity of synchronizing concurrent access to shared data, via the familiar abstraction of atomic transactions. The latter serves to schedule and synchronize the parallel execution of computations whose results are not immediately required. While TM and futures are two widely investigated topics, the problem of how to exploit these two abstractions in synergy is still largely unexplored in the literature. This paper fills this gap by introducing Java Transactional Futures (JTF), a Java-based TM implementation that allows programmers to use futures to coordinate the execution of parallel tasks, while leveraging transactions to synchronize accesses to shared data. JTF provides a simple and intuitive semantic regarding the admissible serialization orders of the futures spawned by transactions, by ensuring that the results produced by a future are always consistent with those that one would obtain by executing the future sequentially. Our experimental results show that the use of futures in a TM allows not only to unlock parallelism within transactions, but also to reduce the cost of conflicts among top-level transactions in high contention workloads.

关键词： concurrent programming Futures Transactional Memory

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Dec :: Pdp11 :: Rt11 :: Micropowerpascal :: Aa-M388A-Tc Introtomicropowerpascal Jan82

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2016年

Dec :: Pdp11 :: Rt11 :: Micropowerpascal :: Aa-M388A-Tc Introtomicropowerpascal Jan82 by published by

关键词： aa-m388a-tc application concurrent concurrent programming file type introtomicropowerpascal jan82 kernel memory memory image micropowerpascal object module object modules pascal pdp11 process process control processes program semaphore source code static process target target system utility programs

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PhTM*: uma implementação eficiente de transações em fases

PhTM*: uma implementação eficiente de transações em fase...

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作者： Carvalho, João Paulo Labegalini de Universidade Estadual Paulista

As evidentes limitações em se explorar o aumento de frequência e otimização no nível de microarquitetura para obtenção de desempenho levaram a indústria de microprocessador... 详细信息

As evidentes limitações em se explorar o aumento de frequência e otimização no nível de microarquitetura para obtenção de desempenho levaram a indústria de microprocessadores a buscar alternativas para suprir tal demanda. A solução encontrada foi construir arquiteturas com múltiplos fluxos de execução (multicore). No entanto, a utilização imediata do modelo paralelo exige que os programadores precisem explicitamente codificar as aplicações de forma a usar todos os núcleos, tarefa essa nada trivial e passível de erros que, muitas vezes, são difíceis de serem detectados. Um novo modelo de programação concorrente conhecido como memória transacional (Transactional Memory – TM) oferece abstrações para fácil codificação de aplicações e é capaz de explorar o paralelismo das arquiteturas multicore sem exigir conhecimentos da arquitetura por parte do programador. Porém, as implementações desse modelo, em software ou hardware, isoladamente apresentam problemas que limitam a escalabilidade das aplicações. Objetivando resolver tais problemas, foram propostos sistemas híbridos de transações em hardware e software para melhor exploração do paralelismo, denominado Memória Transacional Híbrida (Hybrid Transactional Memory – HyTM). A flexibilidade dos sitemas híbridos convencionais, mesmo permitindo executar transações em hardware e software simultaneamente, reduzem o desempenho de ambos seus componentes e tornam mais complexa a implementação da componente em software. Nesse sentido, este trabalho apresenta a primeira implementação eficiente (PhTM*) de um sistema de transações em fases, proposto como alternativa aos HyTMs convencionais. O PhTM* elimina a instrumentação das transações em hardware, necessária em outros HyTMs, e permite utilizar qualquer STM, sem nenhuma modificação, para executar as transações em software. A proposta é a primeira a utilizar o suporte transacioal em hardware disponível em um processador real (não-emulado), para executar as transações em hardware. Os re

关键词： Programação concorrente Memória transacional Sistemas híbridos Fases do programa concurrent programming Transactional memory Hybrid systems Program phase Dissertação de mestrado

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Server for SQLite Database: Multithreaded HTTP Server with Synchronized Database Access and JSON Data-Interchange

Server for SQLite Database: Multithreaded HTTP Server with S...

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International Conference on Advanced Communication Technology

作者： Noprianto Benfano Soewito Sani Muhamad Isa Karto Iskandar Ford Lumban Gaol Raymond Kosala Doctor of Computer Science Bina Nusantara University Master in Computer Science Bina Nusantara University School of Computer Science Bina Nusantara University

ISBN: (纸本)9781509048922

SQLite database engine is small, fast, reliable, and does not need a server to work. And, if needed, multiple applications may work with same SQLite database, optionally, using filesystem sharing services. However, file sharing option is not always available and reliable in certain conditions. In this paper, we propose a server for SQLite database. This server will be using HTTP as communication protocol. To enable multiuser application, this server will be multithreaded. However, access to the database file will be synchronized to help prevent database corruption. And, as data-interchange format, JSON will be used. We also run several tests to make sure that proposed server is usable. Test results show that the database file is not corrupted, while still maintain acceptable performance.

关键词： Embedded database Database server HTTP server concurrent programming Multithreaded application

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User accessible reply capabilities in invoking and servicing operations

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CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2015年第17期27卷 5134-5155页

作者： Olsson, Ronald A. Keen, Aaron W. Univ Calif Davis Dept Comp Sci Davis CA 95616 USA Calif Polytech State Univ San Luis Obispo Dept Comp Sci San Luis Obispo CA 93407 USA

Many message passing languages and packages include some form of synchronous invocation. In a synchronous invocation, the invoker waits for the invocation's servicer to pass back results. A synchronous invocation can be viewed as a pair of asynchronous invocations: one-initiating the computation-with parameter values from the invoker to the servicer and the other-once the requested computation has completed-with the 'go-ahead' and return value from the servicer to the invoker. The target of the latter invocation is known as the reply operation, and a reference to it is known as a reply capability. This paper addresses the issues of making such reply capabilities directly accessible to user code. It presents the design and prototype implementation of a new version of the JR concurrent programming language, called xJR, in which the reply capability can be explicit. This paper gives xJR examples, including realistic ones, to highlight the additional flexibility the new features offer (such as a non-lexical reply). These additional features do not impact the run-time performance of existing JR features and can even lead to more efficient code in some programming scenarios. Our experience with the prototype implementation indicates that an actual implementation would be fruitful and would preserve the prototype's performance advantages. Copyright (c) 2015John Wiley & Sons, Ltd.

关键词： concurrent programming message passing early reply deferred reply forward reply capabilities transformations JR programming language

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Loop Optimization for Divergence Reduction on GPUs with SIMT Architecture

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2015年第6期26卷 1633-1642页

作者： Novak, Roman Jozef Stefan Inst Dept Commun Syst SI-1000 Ljubljana Slovenia

The single-instruction multiple thread (SIMT) architecture that can be found in some latest graphical processing units (GPUs) builds on the conventional single-instruction multiple data (SIMD) parallelism while adopting the thread programming model. The architecture suffers from a degraded performance caused by the inefficient divergence handling, a problem hidden by the programmer's view of independent threads. A loop optimization technique having the potential to increase efficiency of the core SIMD block while processing embedded divergences is investigated here. concurrent loops are generally not bound to iterate in lock-step, allowing better alignment of thread flows via iteration scheduling. The concept efficiency is analyzed for fixed and flow-adapting scheduling policies. The proposed payoff model captures loop overhead implications, allowing one to assess the tradeoffs of applying the technique to a specific loop instance. Processing speedups can generally be observed in the total running time if kernels are compute-bound, as demonstrated by several examples. The studied iteration scheduling policies do not impose alterations to the core SIMD concept and design, thus preserving the benefits of data level parallelism.

关键词： concurrent programming efficiency analysis iteration scheduling multithreaded processors optimization SIMT

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On-Chip Active Messages for Speed, Scalability, and Efficiency

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2015年第2期26卷 507-515页

作者： Harting, R. Curtis Dally, William J. Stanford Univ Dept Elect Engn Stanford CA 94305 USA Nvidia Santa Clara CA USA Stanford Univ Dept Comp Sci Stanford CA 94305 USA

This paper describes and quantifies the benefits of adding low-overhead active messages to many-core, cache-coherent chip-multiprocessors. The active messages we analyze are user defined and trigger the atomic execution of a custom software handler at the destination. Programmers can use these active messages to both move data with less overhead than cache coherency and, more importantly, explicitly send computation to data. Doing so greatly improves (11 x speed, 4.8 x energy) communication idioms such as shared object modification, reductions, data walks, point-to-point communication, and all-to-all communication. Active messages enhance program scalability: applications using them run 63 percent faster with 11 percent less energy on 256 cores. The relative benefits of active messages grow with larger numbers of cores.

关键词： Parallel architecture parallel processors MIMD processors shared memory concurrent programming

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