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A load-balanced congestion-aware routing algorithm based on time interval in wireless network-on-chip

JOURNAL OF AMBIENT INTELLIGENCE AND HUMANIZED COMPUTING 2019年第7期10卷 2869-2882页

作者： Mamaghani, Shokoofeh Mikaeeli Jamali, Mohammad Ali Jabraeil Islamic Azad Univ Dept Comp Engn Tabriz Branch Tabriz Iran Islamic Azad Univ Dept Comp Engn Shabestar Branch Shabestar Iran

Network-on-chip (NoC) has been introduced to increase the performance of chip multiprocessors (CMPs) and execute parallel programs. Although NoC is known as a modular and scalable infrastructure for interconnections, there are still some challenges with conventional NoC such as high latency and power consumption due to the communication among long-distance (LD) cores. In this regard, wireless network-on-chip (WiNoC) is a potential solution that can provide high bandwidth and low latency by means of the unique features of wireless interconnects. However, wireless routers (WRs) are prone to congestion in WiNoC due to the limited number of wireless channels on a chip and shared use of these channels by all processing elements (PEs). In this study, a load-balanced time-based congestion-aware (LTCA) routing algorithm is proposed to eliminate the congestion of WRs and distribute the traffic load on the wired and wireless networks in a balanced way. LTCA is a deadlock-free routing algorithm in which only a limited number of packets are allowed to use wireless channels. The required time for transmitting the selected packets through wireless links is measured with regard to the bandwidth of the wireless channels and traffic load. Simulation results on synthetic traffic patterns and real-world 3-tuple traffic patterns indicated a considerable improvement in latency, throughput, wired and wireless link utilization and packet loss probability.

关键词： congestion-aware routing algorithm Wireless network-on-chip Time interval LTCA

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Reliable congestion-aware path prediction mechanism in 2D NoCs based on EFuNN

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JOURNAL OF SUPERCOMPUTING 2018年第11期74卷 6102-6125页

作者： Rezaei-Ravari, Maryam Sattari-Naeini, Vahid Kerman Grad Univ Adv Technol Dept Comp Engn Kerman Iran Shahid Bahonar Univ Kerman Dept Comp Engn Kerman Iran

The efficiency of networks-on-chip (NoC) is affected by related routing algorithms. This paper aims to develop a reliable routing mechanism in 2D mesh-based NoCs based on evolving fuzzy neural network (EFuNN). Inspiring the advantages of the neural network and the fuzzy system, EFuNN is used for training the network. Online training of EFuNN is faster than that of conventional neural networks trained by the backpropagation algorithm. The proposed algorithm examines distance to the destination, network traffic status, and link faults of the area around the current switch obtaining the reliability metric;it chooses the best path from available paths using fuzzy neural network. Training the network to respond to the routing requests at a specific time is an advantage of using EFuNN. Experimental results show that the on-chip network utilizing the proposed method outperforms state-of-the-art research works in terms of reliability, latency, and throughput regarding different traffic patterns for various 2D mesh topologies.

关键词： Network-on-chip congestion-aware routing algorithm Reliability Evolved fuzzy neural network

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Dynamic clustering-based routing scheme for 2D-Mesh networks-on-chip

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MICROELECTRONICS JOURNAL 2018年 81卷 123-136页

作者： Rezaei-Ravari, Maryam Sattari-Naeini, Vahid Kerman Grad Univ Adv Technol Dept Comp Engn Kerman Iran Shahid Bahonar Univ Kerman Dept Comp Engn Kerman Iran

The efficiency of Networks on Chip (NoC) is affected by related routing algorithms. Moreover, clustering can be utilized to improve the performance of the related routing algorithm. Since traffic type of a system on chip may change with time, dynamic clustering is required to deal with this issue. In this paper, a dynamic clustering-based routing algorithm is proposed utilizing Evolved Fuzzy-Neural Networks (EFuNN) architecture. In the proposed approach, the nodes that have the highest communication among them are grouped into the same cluster. Cluster formation dynamically changes depending on the type of traffic applied to the network. The related reliable routing algorithm splits into two categories;while intra-cluster routing mechanism varies according to the applied traffic type, inter-cluster routing mechanism operates based on EFuNN. Experimental results show that the on-chip network utilizing the proposed method outperforms state-of-the-art research works in terms of reliability, latency, and throughput regarding different traffic patterns for various 2D-mesh topologies.

关键词： Network-on-Chip Reliability Dynamic clustering congestion-aware routing algorithm EFuNN

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Low Latency Path Prediction Mechanism in 2D-NoC 26

Low Latency Path Prediction Mechanism in 2D-NoC

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26th Iranian Conference on Electrical Engineering (ICEE)

作者： Rezaei-Ravari, Maryam Sattari-Naeini, Vahid Kerman Grad Univ Adv Technol Comp Engn Dept Sci Kerman *** Iran Shahid Bahonar Univ Kerman Comp Engn Dept Kerman *** Iran

ISBN: (纸本)9781538649169

Network-on-Chip (NoC) has an efficient on-chip communication solution for Chip Multi-Processors (CMPs) in order to overcome traditional bus connections. One of the disadvantages of congestion in the NoC is increasing the latency. Therefore, congestion-aware routing algorithms are proposed for decreasing the latency. This paper aims to develop a congestion aware routing mechanism for 2D mesh-based NoCs based on Evolving Fuzzy Neural Network (EFuNN). Inspiring the advantages of the Neural Network and the fuzzy system, EFuNN has been used for training the network. The algorithm examines network traffic status and chooses the best path from the available paths using Fuzzy Neural Network. Using this algorithm, the traffic is distributed through the areas that are less congested. Experimental results show that the on-chip network utilizing the proposed method outperforms state-of-theart research works in terms of latency regarding different traffic patterns for various 2D-mesh topologies.

关键词： Network-on-Chip congestion-aware routing algorithm Evolved Fuzzy Neural Network

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Low Latency Path Prediction Mechanism in 2D-NoC

Low Latency Path Prediction Mechanism in 2D-NoC

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Iranian Conference on Electrical Engineering

作者： Maryam Rezaei-Ravari Vahid Sattari-Naeini Computer Engineering Department Kerman Graduate University of Advanced Technology Kerman Iran

Network-on-Chip (NoC) has an efficient on-chip communication solution for Chip Multi-Processors (CMPs) in order to overcome traditional bus connections. One of the disadvantages of congestion in the NoC is increasing the latency. Therefore, congestion-aware routing algorithms are proposed for decreasing the latency. This paper aims to develop a congestion-aware routing mechanism for 2D mesh-based NoCs based on Evolving Fuzzy Neural Network (EFuNN). Inspiring the advantages of the Neural Network and the fuzzy system, EFuNN has been used for training the network. The algorithm examines network traffic status and chooses the best path from the available paths using Fuzzy Neural Network Using this algorithm, the traffic is distributed through the areas that are less congested. Experimental results show that the on-chip network utilizing the proposed method outperforms state-of-the-art research works in terms of latency regarding different traffic patterns for various 2D-mesh topologies.

关键词： Network-on-Chip congestion-aware routing algorithm Evolved Fuzzy Neural Network

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Adaptive load balancing in learning-based approaches for many-core embedded systems

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JOURNAL OF SUPERCOMPUTING 2014年第3期68卷 1214-1234页

作者： Farahnakian, F. Ebrahimi, M. Daneshtalab, M. Liljeberg, P. Plosila, J. Univ Turku Turku Finland

Adaptive routing algorithms improve network performance by distributing traffic over the whole network. However, they require congestion information to facilitate load balancing. To provide local and global congestion information, we propose a learning method based on dual reinforcement learning approach. This information can be dynamically updated according to the changing traffic condition in the network by propagating data and learning packets. We utilize a congestion detection method which updates the learning rate according to the congestion level. This method calculates the average number of free buffer slots in each switch at specific time intervals and compares it with maximum and minimum values. Based on the comparison result, the learning rate sets to a value between 0 and 1. If a switch gets congested, the learning rate is set to a high value, meaning that the global information is more important than local. In contrast, local is more emphasized than global information in non-congested switches. Results show that the proposed approach achieves a significant performance improvement over the traditional Q-routing, DRQ-routing, DBAR and Dynamic XY algorithms.

关键词： congestion-aware routing algorithm Adaptive routing algorithm Q-learning and Q-routing approaches

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Bi-LCQ: A low-weight clustering-based Q-learning approach for NoCs

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MICROPROCESSORS AND MICROSYSTEMS 2014年第1期38卷 64-75页

作者： Farahnakian, F. Ebrahimi, M. Daneshtalab, M. Liljeberg, P. Plosila, J. Univ Turku Dept Informat Technol Turku Finland

Network congestion has a negative impact on the performance of on-chip networks due to the increased packet latency. Many congestion-aware routing algorithms have been developed to alleviate traffic congestion over the network. In this paper, we propose a congestion-aware routing algorithm based on the Q-learning approach for avoiding congested areas in the network. By using the learning method, local and global congestion information of the network is provided for each switch. This information can be dynamically updated, when a switch receives a packet. However, Q-learning approach suffers from high area overhead in NoCs due to the need for a large routing table in each switch. In order to reduce the area overhead, we also present a clustering approach that decreases the number of routing tables by the factor of 4. Results show that the proposed approach achieves a significant performance improvement over the traditional Q-learning, C-routing, DBAR and Dynamic XY algorithms. (C) 2013 Elsevier B.V. All rights reserved.

关键词： Network-on-Chip congestion-aware routing algorithm Adaptive routing algorithm Q-learning and Q-routing approaches

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Design and management of high-performance, reliable and thermal-aware 3D networks-on-chip

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IET CIRCUITS DEVICES & SYSTEMS 2012年第5期6卷 308-321页

作者： Rahmani, A. -M. Vaddina, K. R. Latif, K. Liljeberg, P. Plosila, J. Tenhunen, H. Univ Turku Dept Informat Technol Embedded Comp & Elect Syst Lab FIN-20520 Turku Finland Turku Ctr Comp Sci TUCS Turku 20520 Finland

Increasing the number of cores over a 2D plane is not efficient in hyper-core systems due to long interconnects. As a viable alternative over the 2D planar chip, 3D integrated technology offers greater device integration and shorter interlayer interconnects. 3D networks-on-chip (NoC)-bus hybrid mesh architecture, which is a hybrid between packet-switched network and a bus, was proposed to take advantage of the intrinsic attributes of 3D ICs. Even though this architecture was proposed as a feasible one to provide both performance and area benefits, the challenges of combining both media (NoC and bus) to design 3D NoCs have not been addressed. In this study, an efficient 3D NoC architecture is proposed to optimise performance, power consumption and reliability of 3D NoC-bus hybrid mesh system. The mechanism benefits from a congestion-aware and bus failure tolerant routing algorithm called 'AdaptiveZ' for vertical communication. In addition, the authors propose thermal-aware scheduling strategy in order to mitigate temperature by herding most of the switching activity closer to the heatsink. To estimate the efficiency of the proposed architecture, the system has been simulated using uniform, hotspot 10% and negative exponential distribution traffic patterns. In addition, a videoconference encoder has been used as a real application for system analysis. Compared with a typical stacked mesh 3D NoC, our extensive simulations demonstrate significant power, performance and peak temperature improvements.

关键词： packet-switched network AdaptiveZ routing algorithm 3D IC congestion-aware routing algorithm integrated circuit reliability switching activity 3D NoC-bus hybrid mesh architecture 3D integrated technology typical stacked mesh 3D NoC videoconference encoder 2D planar chip video communication device integration high-performance 3D network-on-chip vertical communication temperature mitigation bus failure tolerant routing algorithm thermal-aware 3D network-on-chip three-dimensional integrated circuits encoding thermal-aware scheduling strategy power consumption network routing scheduling teleconferencing negative exponential distribution traffic patterns hyper-core systems network-on-chip 3D network-on-chip reliability interlayer interconnects

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Optimized Q-learning Model for Distributing Traffic in On-Chip Networks

Optimized Q-learning Model for Distributing Traffic in On-Ch...

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IEEE 3rd International Conference on Networked Embedded Systems for Every Application (NESEA)

作者： Farahnakian, Fahimeh Ebrahimi, Masoumeh Daneshtalab, Masoud Plosila, Juha Liljeberg, Pasi Univ Turku Dept Informat Technol Turku Finland

ISBN: (纸本)9781467347211

Many adaptive routing protocols have been developed for Networks -on-Chip to improve the network performance by traffic reduction. In this paper, we present an adaptive routing algorithm based upon the Q-routing, which distributes traffic by a learning method in the entire network. The learning method utilizes local and global traffic information and can select the minimum latency path to the destination. Since the routing table sizes become one of the main sources of area consumption in the Q-routing algorithm, we propose a clustering approach in order to reduce the area overhead. Furthermore, this approach improves the observability of the traffic condition. Experimental results for different traffic patterns and network loads show that the proposed method achieves significant performance improvement over the Q-routing, C-routing, DBAR and Dynamic XY algorithms.

关键词： Network-on-Chip Adaptive routing algorithm congestion-aware routing algorithm Q-routing

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