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context-adaptive binary arithmetic coding with precise probability estimation and complexity scalability for high-efficiency video coding

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JOURNAL OF ELECTRONIC IMAGING 2016年第1期25卷 1-16页

作者： Karwowski, Damian Domanski, Marek Poznan Univ Tech PL-60965 Poznan Poland

An improved context-based adaptive binary arithmetic coding (CABAC) is presented. The idea for the improvement is to use a more accurate mechanism for estimation of symbol probabilities in the standard CABAC algorithm. The authors' proposal of such a mechanism is based on the context-tree weighting technique. In the framework of a high-efficiency video coding (HEVC) video encoder, the improved CABAC allows 0.7% to 4.5% bitrate saving compared to the original CABAC algorithm. The application of the proposed algorithm marginally affects the complexity of HEVC video encoder, but the complexity of video decoder increases by 32% to 38%. In order to decrease the complexity of video decoding, a new tool has been proposed for the improved CABAC that enables scaling of the decoder complexity. Experiments show that this tool gives 5% to 7.5% reduction of the decoding time while still maintaining high efficiency in the data compression. (C) 2016 SPIE and IS&T

关键词： video compression advanced video coding high-efficiency video coding entropy coding context-based adaptive binary arithmetic coding improved context-based adaptive binary arithmetic coding

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Field programmable gate array implementation of variable-bins high efficiency video coding CABAC decoder with path delay optimisation

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IET IMAGE PROCESSING 2019年第6期13卷 954-963页

作者： Menasri, Wahiba Skoudarli, Abdellah Belhadj, Aichouche Azzaz, Mohamed Salah USTHB Fac Elect & Informat BP 32 El Alia Bab Ezzouar Algiers Algiers Algeria Ecole Mil Polytech BP 17 Bordj El Bahri Algiers Algeria

context-based adaptive binary arithmetic coding (CABAC) is a single operation mode for entropy coding in the last video coding standard high-efficiency video coding. For high-resolution applications, the throughput of one bin/cycle is not sufficient and it is a very challenging task to implement pipeline and/or parallel CABAC decoding architecture by simply adding more stages. Indeed, the tight data dependencies make it difficult to parallelise and cause it to be a throughput bottleneck for video decoding. Consequently, in order to improve the CABAC decoder throughput, parallel and pipeline architectures are used in authors' design. In this work, an algorithm-architecture adequation is proposed to implement a CABAC decoder on a field programmable gate array. Mainly, a new classification of 32 syntax elements is given to speed up the authors' solution. Furthermore, the context selection and modelling of regular syntax elements are studied, designed and implemented. Finally, a novel technique of memories rearrangement to reduce the critical path delay required to process each binary symbol is proposed. As a result, the implementation can process 2.2 bins/cycle when operated at 123.49 MHz and exhibits an improved high-throughput of 271.678 Mbins/s. The hardware architecture is coded using hardware description language and synthesised using ISE Xilinx tools targeting the Virtex4 platform.

关键词： arithmetic codes binary codes adaptive codes entropy codes field programmable gate arrays video coding decoding hardware description languages high-throughput field programmable gate array implementation variable-bins high efficiency video coding CABAC decoder path delay optimisation context-based adaptive binary arithmetic coding single operation mode entropy coding video coding standard high-efficiency video coding high-resolution applications bin/cycle CABAC decoding architecture throughput bottleneck video decoding CABAC decoder throughput pipeline architectures algorithm-architecture adequation critical path delay 2.2 bins/cycle frequency 123.49 MHz

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Double bit range estimation with eight estimators for CABAC in VVC

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IET IMAGE PROCESSING 2022年第12期16卷 3155-3163页

作者： Chan, Ka-Hou Im, Sio-Kei Macao Polytech Univ Fac Appl Sci Taipa Macau Peoples R China Macao Polytech Univ Taipa Macau Peoples R China

This work describes the modification of context-based adaptive binary arithmetic coding (CABAC) using the double bit range estimation in the VVC engine and the consideration of range updates by using eight hypothetical probability estimators. The focus is on the selected adaptation rates performed in these proposed estimators, which are chosen based on memory consideration and coding efficiency. An investigation of arithmetic coding engines with multi-hypothesis probability estimates and their consideration of contextual modeling of entropy coding at the level of transform coefficients. The proposed scheme enables a quantitative representation of probabilistic predictions linearly and describes the scalability potential for higher accuracy. In addition, this work discusses the hardware implementation, which is based on simple operations such as bitwise operations and subinterval updates. The experimental results validate the effectiveness of the proposed approach specified in VTM framework. The improved results show that it provides more significant gains in terms of RA and LD, which is better than the AI configuration.

关键词： hypothetical probability estimators memory consideration VVC engine probability arithmetic coding engines context-based adaptive binary arithmetic coding double bit range estimation multihypothesis probability estimates binary codes entropy coding entropy codes range updates selected adaptation rates coding efficiency CABAC adaptive codes arithmetic codes video coding

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Architecture Design of Fine Grain Quality Scalable Encoder with CABAC for H.264/AVC Scalable Extension

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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2010年第3期60卷 363-375页

作者： Chuang, Tzu-Der Chen, Yu-Jen Chen, Yi-Hau Chien, Shao-Yi Chen, Liang-Gee Natl Taiwan Univ 1 Dept Elect Engn 2 Taipei 10617 Taiwan

In addition to coding efficiency, the scalable extension of H. 264/AVC provides good functionality for video adaptation in heterogeneous environments. Fine grain scalability (FGS) is a technique to extract video bitstream at the finest quality level under the given bandwidth. In this paper, an architecture of FGS encoder with low external memory bandwidth and low hardware cost is proposed. Up to 99% of bandwidth reduction can be attained by the proposed scan bucket algorithm, early context modeling with context reduction, and first scan pre-encoding. The area-efficient hardware architecture is implemented by layer-wise hardware reuse. Besides, three design strategies for enhancement layer coder are explored so that the trade-off between external memory bandwidth and silicon area is allowed. The proposed hardware architecture can real-time encode HDTV 1920x1080 video with two FGS enhancement layers at 200 MHz working frequency, or HDTV 1280x720 video with three FGS enhancement layers at 130 MHz working frequency.

关键词： FGS Quality scalability Scalable video coding H.264/AVC context-based adaptive binary arithmetic coding

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Architecture Design of Fine Grain Quality Scalable Encoder with CABAC for H.264/AVC Scalable Extension

Architecture Design of Fine Grain Quality Scalable Encoder w...

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IEEE Workshop on Signal Processing Systems

作者： Chuang, Tzu-Der Chen, Yu-Jen Chen, Yi-Hau Chien, Shao-Yi Chen, Liang-Gee Natl Taiwan Univ 1 Dept Elect Engn 2 Taipei 10617 Taiwan

关键词： FGS Quality scalability Scalable video coding H.264/AVC context-based adaptive binary arithmetic coding

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Architecture design of fine grain SNR scalable encoder with CABAC for H.264/AVC scalable extension

Architecture design of fine grain SNR scalable encoder with ...

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IEEE Workshop on Signal Processing Systems

作者： Chen, Yu-Jen Chen, Yi-Hau Chuang, Tzu-Der Li, Chung-Te Chien, Shao-Yi Chen, Liang-Gee Natl Taiwan Univ Grad Inst Elect Engn Taipei 10617 Taiwan

ISBN: (纸本)9781424412211

In addition to coding efficiency, the scalable extension of H.264/AVC provides good functionality for the adaptation in heterogeneous environments. Fine grain scalability (FGS) is a technique to extract video at the best quality level under the available bandwidth. In this paper, an architecture of FGS encoder with low external memory bandwidth and low hardware costs is developed. At most 92% bandwidth reduction can be attained by the proposed scan bucket algorithm, early context modeling with context reduction, and first scan pre-encoding. The area-efficient architecture is implemented by layer-wise hardware reuse, and three design strategies for enhancement layer coder are explored so that the trade-off between external memory bandwidth and silicon area is allowed. This design can real-time encode HDTV 1280x720 video at 130 MHz working frequency.

关键词： FGS fine grain scalability SNR scalability SVC scalable video coding H.264/AVC scalable extension CABAC context-based adaptive binary arithmetic coding

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