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IEEE 20th International On-Line Testing Symposium (IOLTS)

作者： Du, B. Reorda, M. Sonza Sterpone, L. Parra, L. Portela-Garcia, M. Lindoso, A. Entrena, L. Politecn Torino Dipartimento Automat & Informat Turin Italy Univ Carlos III Madrid Dept Elect Technol Madrid Spain

ISBN: (纸本)9781479953240

Transient faults can affect the behavior of electronic systems, and represent a major issue in many safety-critical applications. This paper focuses on control flow Errors (CFEs) and extends a previously proposed method, based on the usage of the debug interface existing in several processors/controllers. The new method achieves a good detection capability with very limited impact on the system development flow and reduced hardware cost: moreover, the proposed technique does not involve any change either in the processor hardware or in the application software, and works even if the processor uses caches. Experimental results are reported, showing both the advantages and the costs of the method.

关键词： on-line test debug interface control flow checking

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Software-based control flow Error Detection and Correction Using Branch Triplication

Software-based Control Flow Error Detection and Correction U...

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17th IEEE International On-Line Testing Symposium (IOLTS)

作者： Ghalaty, Nahid Farhady Fazeli, Mahdi Rad, Hossein Izadi Miremadi, Seyed Ghassem Sharif Univ Technol Dept Comp Engn Azadi Ave Tehran Iran

ISBN: (纸本)9781457710551

Ever Increasing use of commercial off-the-shelf (COTS) processors to reduce cost and time to market in embedded systems has brought significant challenges in error detection and recovery methods employing in such systems. This paper presents a software based control flow error detection and correction technique, so called branch TMR (BTMR), suitable for use in COTS-based embedded systems. In BTMR method, each branch instruction is triplicated and a software interrupt routine is invoked to check the correctness of the branch instruction. During the execution of a program, when a branch instruction is executed, it is compared with the second redundant branch in the interrupt routine. If a mismatch is detected, the third redundant branch instruction is considered as the error-free branch instruction;otherwise, no error has occurred. The main advantage of BTMR over previously proposed control flow checking (CFC) methods is its ability to correct CFEs as well as protection of indirect branch instructions. The BTMR method is evaluated on LEON2 embedded processor. The results show that, error correction coverage is about 96%, while memory overhead and performance overhead of BTMR is about 28% and 10%, respectively.

关键词： control flow checking COTS processor fault tolerance software-based error detection error correction

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EXPERIMENTAL RESULTS ON THE ERROR-DETECTION CAPABILITY OF A CONCURRENT TEST ARCHITECTURE FOR MASSIVELY-PARALLEL COMPUTERS

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PARALLEL COMPUTING 1992年第10期18卷 1079-1103页

作者： HANCU, MVA IWASAKI, K SATO, Y SUGIE, M CHIBA UNIV FAC ENGNDEPT INFORMAT & COMP SCICHIBA 260JAPAN HITACHI LTD CENT RES LABKOKUBUNJITOKYO 185JAPAN

In a previous paper, we introduced a new concurrent testing (or on-line monitoring) architecture for Massively-Parallel Computers. In the proposed test architecture, on-line checks for both control flow and data Touting are accomplished by enforcing the run-time test of compressed (signatured) versions of the control and data dependences of the algorithm executed in the parallel computer. This paper focuses on the results of simulation experiments on the error detection of the proposed test architecture as applied to the routing process. Four sets of experiments were executed, with two compressors or signature analyzers (an MISR and an LFSR) and two error models (the 2m-ary and the Binary Symmetric Channel). Using a randomized routing process and a randomized fault insertion, we have obtained detailed figures for the undetected errors at all crucial detecting points of our proposed detection method: the source, the expected destination and the false destination of the messages. High detection ratios for multiple errors were obtained for compressors of only moderate size, supporting the use of this method in practical applications. The results are independent of the topology of the interconnection network and the detailed routing algorithm.

关键词： ALIASING PROBABILITY CONCURRENT TESTING control flow checking DATA DEPENDENCE checking MASSIVELY-PARALLEL COMPUTERS ONLINE ERROR-DETECTION, PACKET-SWITCHED ROUTING PARALLEL COMPUTING SIGNATURE ANALYSIS SYSTEM-LEVEL ERROR DETECTION

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Tolerating Radiation-Induced Transient Faults in Modern Processors

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INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING 2010年第2期38卷 85-116页

作者： Li, Xiaobin Gaudiot, Jean-Luc Intel Corp Enterprise Microprocessor Grp Santa Clara CA 95051 USA Univ Calif Irvine Dept Elect Engn & Comp Sci Irvine CA USA

As MOS device sizes continue shrinking, lower charges, for example those charges carried by single ionizing particles of naturally occurring radiation, are sufficient to upset the functioning of complex modern microprocessors. In order to handle these inevitable errors, designs should include fault-tolerant features so that the processors can continue to correctly perform despite the occurrence of errors. The main goal of this work is to develop architecture mechanisms to protect processors against the effect of such radiation-induced transient faults. It should first be noted that, from a program execution perspective, many faults manifest themselves as control flow errors that cause processors to violate the correct sequencing of instructions. We present here at first a basic compile-time signature assignment algorithm and describe a novel approach to improve the fault detection coverage of the basic algorithm. Moreover, to allow the processor to efficiently check the run-time sequence and detect control flow errors, we introduce an on-chip assigned-signature checker which is capable of executing three additional instructions (SIC, SIJ, SIJC). Second, since the very concept of simultaneous multi-threading (SMT) provides the necessary redundancy, some proposals have been made to run two copies of the same thread on top of SMT platforms in order to detect and correct soft errors. This allows, upon detection of an error, the rolling back of the processor state to a known safe point, and then a retry of the instructions, thereby effecting a completely error-free execution. This paper has focused on two crucial implementation issues introduced by this scheme: (1) the design trade-off between the fault detection coverage versus design costs;(2) the possible occurrence of deadlock situations.

关键词： Soft-error Computer architecture Fault-tolerant control flow checking Multi-threading

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A CONCURRENT TEST ARCHITECTURE FOR MASSIVELY-PARALLEL COMPUTERS AND ITS ERROR-DETECTION CAPABILITY

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 1994年第11期5卷 1169-1184页

作者： HANCU, MVA IWASAKI, K SATO, Y SUGIE, M CHIBA UNIV FAC ENGNDEPT INFORMAT & COMP SCICHIBA 260JAPAN HITACHI LTD CENT RES LABKOKUBUNJITOKYO 185JAPAN

This paper presents new principles for the on-line monitoring in the context of multiprocessors (especially massively parallel processors) and then focuses on the effect of the aliasing probability on the error detection process. In the proposed test architecture, the concurrent testing (or on-line monitoring) at system level is accomplished by enforcing the runtime test of the data and control dependences of the algorithm currently executed in the parallel computer. In order to help in this process, each message contains both source and destination addresses. At each message source, the sequence of destination addresses of the outgoing messages is compressed on a block basis. At the same time, at each destination;the sequence of source addresses of all incoming messages is compressed, also on a block basis. Concurrent compression of the instructions executed by the PE's is also possible. As a result of this procedure, an image of the data dependences and bf the control flow of the currently run algorithm is created. This image is compared at the end of each computational block with a reference image created at compilation time. The main results of this work are in proposing new principles for the on-line system-level test of multiprocessors systems,based on signaturing and monitoring the data dependences together with the control dependences, and in providing an analytical model and analysis for the address compression process used for the monitoring the data routing process.

关键词： ALIASING PROBABILITY CONCURRENT TESTING control flow checking DATA DEPENDENCE checking MASSIVELY PARALLEL COMPUTERS ONLINE ERROR-DETECTION PACKET-SWITCHED ROUTING PARALLEL COMPUTING SIGNATURE ANALYSIS SYSTEM-LEVEL ERROR DETECTION

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Software implemented transient fault detection in space computer

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AEROSPACE SCIENCE AND TECHNOLOGY 2007年第2-3期11卷 245-252页

作者： Li, Aiguo Hong, Bingrong Harbin Inst Technol Sch Comp Sci & Technol Harbin 150001 Peoples R China

Computer systems operating in space environment are subject to different radiation phenomena, whose effects are often called "Soft Error". Generally, these systems employ hardware techniques to address soft-errors, however, software techniques can provide a lower-cost and more flexible alternative. This paper presents a novel, software-only, transient-fault-detection technique, which is based on a new control flow checking scheme combined with software redundancy. The distinctive advantage of our approach over other fault tolerance techniques is the lower performance overhead with the higher fault coverage. It is able to cope with transient faults affecting data and the program control flow. By applying the proposed technique on several benchmark applications, we evaluate the error detection capabilities by means of several fault injection campaigns. Experimental results show that the proposed approach can detect more than 98% of the injected bit-flip faults with a mean execution time increase of 153%. (c) 2006 Elsevier Masson SAS. All rights reserved.

关键词： transient fault control flow checking concurrent error detection fault injection

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Software detection mechanisms providing full coverage against single bit-flip faults

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2004年第6期51卷 3510-3518页

作者： Nicolescu, B Savaria, Y Velazco, R Ecole Polytech Montreal PQ H3T 1J4 Canada TIMA Lab Circuits Qualificat Grp F-38031 Grenoble France

Increasing design complexity for current and future generations of microelectronic technologies leads to an increased sensitivity to transient bit-flip errors. These errors can cause unpredictable behaviors and corrupt data integrity and system availability. This paper proposes new solutions to detect all classes of faults, including those that escape conventional software detection mechanisms, allowing full protection against transient bit-flip errors. The proposed solutions, particularly well suited for low-cost safety-critical microprocessor-based applications, have been validated through exhaustive fault injection experiments performed on a set of real and synthetic benchmark programs. The fault model taken into consideration was single bit-flip errors corrupting memory cells accessible to the user by means of the processor instruction set. The obtained results demonstrate the effectiveness of the proposed solutions.

关键词： control flow checking data computing block (DCB) exhaustive fault injection experiments signature monitoring technique software error detection

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Error detection enhancement in PowerPC architecture-based embedded processors

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JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS 2008年第1-3期24卷 21-33页

作者： Fazeli, Mahdi Farivar, Reza Mirernadi, Seyed Ghassern Sharif Univ Technol Tehran Iran

This paper presents a behavior-based error detection technique called control flow checking using Branch Trace Exceptions for PowerPC processors family (CFCBTE). This technique is based on the branch trace exception feature available in the PowerPC processors family for debugging purposes. This technique traces the target addresses of program branches at run-time and compares them with reference target addresses to detect possible violations caused by transient faults. The reference target addresses are derived by a preprocessor from the source program. To enhance the error detection coverage, three other mechanisms, i.e., Machine Check Exception, System Trap Instructions and Work Load Timer are combined with the Branch Trace Exception mechanism. The proposed technique is experimentally evaluated on a 32-bit PowerPC microcontroller using software implemented fault injection (SWIFI) and Power Supply Disturbances fault injection (PSD). A total of 6,000 faults were injected in microcontroller to measure the error detection coverage of the proposed control flow checking technique. The experimental results show that this technique detects about 95.2% of transient errors in software implemented fault injection method and 96.4% of transient errors in power supply disturbances fault injection method.

关键词： concurrent error detection control flow checking physical fault injection power supply disturbances

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A checkpointing technique for rollback error recovery in embedded systems

A checkpointing technique for rollback error recovery in emb...

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18th International Conference on Microelectronics (ICM 2006)

作者： Bashiri, Mohsen Miremadi, Seyed Ghassem Fazeli, Mahdi Sharif Univ Technol Dept Comp Engn Dependable Syst Lab Tehran Iran

ISBN: (纸本)9781424407644

In this paper, a general Checkpointing technique for rollback error recovery for embedded systems is proposed and evaluated. This technique is independent of used processor and employs the most important feature in control flow error detection mechanisms to simplify checkpoint selection and to minimize the overall code overhead. In this way, during the implementation of a control How checking mechanism, the checkpoints are added to the program. To evaluate the Checkpointing technique, a pre-processor is implemented that selects and adds the checkpoints to three workload programs running in an 8051 microcontroller -based system. The evaluation is based on 3000 experiments for each checkpoint.

关键词： rollback error recovery embedded systems control flow checking checkpoint

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Hardware Runtime Verification of a RTOS Kernel: Evaluation Using Fault Injection 14

Hardware Runtime Verification of a RTOS Kernel: Evaluation U...

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14th European Dependable Computing Conference (EDCC)

作者： Solet, Dimitry Bechennec, Jean-Luc Briday, Mikael Faucou, Sebastien Pillement, Sebastien Univ Nantes IETR UMR 6164 Nantes France CNRS LS2N UMR 6004 Nantes France Univ Nantes CNRS LS2N UMR 6004 Nantes France

ISBN: (纸本)9781538680605

Nowadays complete systems can be built on a System-on-a-Programmable-Chip that integrates a microcontroller and a FPGA fabric into a single chip. Beside its traditional use to implement hardware accelerators, the FPGA can be used to monitor the software running on the microcontroller with a very small overhead. In this work, we investigate the case of monitoring safety properties. We have synthesized a runtime verification system to verify a part of the behavior of a real-time operating system. The paper presents the coverage provided by this approach with regards to transient hardware faults. The evaluation is based on an ISA-level fault injection campaign.

关键词： Fault injection real-time system runtime verification RTOS control flow checking

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