New open box and nonlinear model of Ultra High Frequency Polynomial and Sine Artificial Higher Order Neural Network (UPS-HONN) is presented in this paper. A new learning algorithm for UPS-HONN is also developed from t...
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ISBN:
(纸本)9781479945306
New open box and nonlinear model of Ultra High Frequency Polynomial and Sine Artificial Higher Order Neural Network (UPS-HONN) is presented in this paper. A new learning algorithm for UPS-HONN is also developed from this study. A controlsignal generating system, UPS-HONN Simulator, is built based on the UPS-HONN models. Test results show that, to generate any nonlinear controlsignal, average error of UPS-HONN models is under 1e-6.
In traditional low-frequency energy harvesting circuits, a large matched inductor with a large size is unavoidable. To reduce the size of the circuit, this paper proposes a compact self-powered inductor-less high-effi...
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In traditional low-frequency energy harvesting circuits, a large matched inductor with a large size is unavoidable. To reduce the size of the circuit, this paper proposes a compact self-powered inductor-less high-efficiency piezoelectric energy harvesting circuit using a low-power-consumption gyrator. A self-powered floating gyrator inductor is used in place of an inductor in the proposed circuit, and the required phasor response is acquired by using its voltage-current (V-I) relationship. The proposed circuit offers easy adjustability and performance benefits in small integrated circuits packages. The proposed circuit can be cost-effective and provide reduced area advantages in autonomous self-powered Internet-of-Things and wireless sensor nodes applications. Regarding harvested energy, the proposed circuit with a storage capacitor of 0.24 F can obtain 320% improved performance than standard energy harvesting along with the lowest power consumption of 0.25 mu W in self-powered operation. The proposed technique can also be applied to similar piezoelectric energy harvesting strategies with large inductors.
This note studies implementation issues arising in observer-based controllers acting under intermittent information exchange between their sensor-and actuator-side parts. Existing implementation schemes assume that a ...
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This work presents a dynamic width segmentation scheme of the power MOSFETs to improve the light load efficiency in high frequency DC-DC converters. The proposed scheme first senses the load current and decides the ma...
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ISBN:
(纸本)9781479925124
This work presents a dynamic width segmentation scheme of the power MOSFETs to improve the light load efficiency in high frequency DC-DC converters. The proposed scheme first senses the load current and decides the maximum number of power MOSFET segments to be turned ON. In order to sense the load current accurately over a wide range, an improved current sensing method is also suggested. The proposed scheme is designed and simulated in a 0.5 mu m Bi-CMOS technology. To validate its effectiveness, an integrated system is designed using a monolithic voltage mode, synchronous DC-DC buck converter topology switching at 20 MHz. Only the passive components (L=330 nH and C= 2.2 mu F) are the off-chip components. The input voltage Vin lies in the range of 2.7 V-5.5 V which is quite suitable for Li-ion or Ni-Cd battery operated applications. The output voltage is targeted at 1.2 V and maximum load current specification is 600 mA. The whole power MOSFET is segmented into 16 equal parts and a signal conditioning loop decides the number of active segments dynamically based on the load current. Simulation result shows that at the lightest load of 10 mA, the power efficiency of the converter with and without the dynamic width segmentation scheme is 40% and 19.5% respectively. This shows an efficiency improvement of nearly 103% at the lightest load of 10 mA.
This paper discusses a controller design in high-level synthesis to tolerate multi-cycle transient faults under the situation where its datapath has the ability of tolerating such faults. It focuses especially on the ...
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ISBN:
(纸本)9781479976034
This paper discusses a controller design in high-level synthesis to tolerate multi-cycle transient faults under the situation where its datapath has the ability of tolerating such faults. It focuses especially on the control signal generator (or output logic) that is a component of the controller feeding controlsignals to the datapath in a controller-datapath system, and presents a method of controller synthesis that leverages the error correction/detection ability of the datapath. Experimental results show that the proposed method can synthesize fault tolerant controllers with small area overhead compared with the conventional method based on triple modular redundancy (TMR).
We investigated the setting method of exposure times for an adaptive multi-exposure image fusion. Because the range of luminance in the natural environment is wide and objects in captured image have inherent optical p...
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ISBN:
(数字)9781728137063
ISBN:
(纸本)9781728137070
We investigated the setting method of exposure times for an adaptive multi-exposure image fusion. Because the range of luminance in the natural environment is wide and objects in captured image have inherent optical properties, the vision system need to adapt to the input light. The proposed system comprises an image sensor module and a field-programmable gate array (FPGA) which is composed of control signal generator for an image sensor, HDR (High-dynamic-range) image generator/evaluator. In this study, we employed and evaluated maximum entropy of HDR image as the exposure time setting method.
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