Extracting the fixed point model for digital hardware implementation is an important step in the realization of digital signal processing systems. In such a model, limited word lengths for processing blocks should be ...
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ISBN:
(纸本)9781424458219;9781424458240
Extracting the fixed point model for digital hardware implementation is an important step in the realization of digital signal processing systems. In such a model, limited word lengths for processing blocks should be selected with no harmful effects on the system performance. Viterbi decoder is one of the commonly used blocks in digital communication systems. Optimizing its word length causes a considerable reduction in the chip area and decoding delay. In this paper the Viterbi decoder parameters, i.e. the number of soft decision bits and trace-back depth, are optimized for a new wireless standard, IEEE 802.22. The optimization is performed with less than 0.5 dB degradation of BER of the fixed point model compared to the floating point model. The 64QAM modulation with the code rate 5/6 is selected as a case study since it is the most sensitive mode in the standard to the channel noise. Simulation results show that the Viterbi decoder with 7 bit soft decision and trackback depth of 70 meets the system requirements.
In this paper, we investigate the design procedures of the bit labelling rule as well as the outer channel code for the table-based bit-interleaved coded differential amplitude/phase modulation (BICD-APM) scheme under...
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In this paper, we investigate the design procedures of the bit labelling rule as well as the outer channel code for the table-based bit-interleaved coded differential amplitude/phase modulation (BICD-APM) scheme under correlated Rayleigh fading channels. Based on the asymptotic pairwise error probability (PEP) formula reported in the previous work, the design criteria for the generator polynomials of the outer convolutional encoder, and for the bit labelling strategy of the inner differential modulator, are investigated for the table-based differential APM schemes when considering two different types of bit interleavers. It is shown that the designed scheme which considers parallel bit interleavers is able to achieve the best bit error rate (BER) performance, and provides a significant SNR gain under the same BER value, when compared to the conventional BICD-APM scheme reported in the previous literature.
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