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cordic algorithm for vectoring mode without constant scaling factors

ELECTRONICS LETTERS 1999年第12期35卷 971-972页

作者： Juang, TB Lin, HF Ta Jen Jr Coll Pharm Dept Hlth Adm Ping Tung Cty Taiwan Feng Chia Univ Dept Informat Engn Taichung 40724 Taiwan

A new cordic algorithm is presented that can be used for the vectoring mode without requiring constant scaling Factors. The algorithm can also be used to carry out complete transformation from rectangular co-ordinates (x, y) to polar co-ordinates (rho,theta). In each iteration, the exponent difference of x and y is computed so as to speed up convergence. This new cordic algorithm has an average of 0.75 n iterations for n-bit input data and can achieve > 94.78% 23 bit accuracy. It is also suitable for VLSI chip implementation due to the regular architecture required.

关键词： convergence Digital arithmetic methods digital arithmetic iteration co-ordinate transformation VLSI chip cordic algorithm vectoring mode

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cordic algorithm based digital detection technique applied in resonator fiber optic gyroscope

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OPTICAL FIBER TECHNOLOGY 2009年第3期15卷 328-331页

作者： Yang, Zhihuai Jin, Xiaojun Ma, Huilian Jin, Zhonghe Zhejiang Univ Dept Informat Sci & Elect Engn Hangzhou 310027 Zhejiang Peoples R China

A digital detection technique based on the coordinate rotation digital computer (cordic) algorithm is proposed for a resonator fiber optic gyroscope (R-FOG). It makes the generation of modulation signal, synchronous demodulation and signal processing in R-FOG to be realized in a single field programmable gate array (FPGA). The frequency synthesis and synchronous detection techniques based on the cordic algorithm have been analyzed and designed firstly. The experimental results indicate that the precision of the detection circuit satisfies the requirements for the closed-loop feedback in R-FOG system. The frequency of the laser is locked to the resonance frequency of the fiber ring resonator stably and the open-loop gyro output signal is observed successfully. The dynamic range and the bias drift of the R-FOG are +/- 1.91 rad/s and 0.005 rad/s over 10 s, respectively. (C) 2009 Elsevier Inc. All rights reserved.

关键词： Resonator fiber optic gyroscope cordic algorithm Synchronous demodulation Digitalization

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Redundant Floating-Point Decimal cordic algorithm

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IEEE TRANSACTIONS ON COMPUTERS 2012年第11期61卷 1551-1562页

作者： Vazquez, Alvaro Villalba-Moreno, Julio Antelo, Elisardo Zapata, Emilio L. Univ Santiago Dept Elect & Comp Sci Santiago Spain Univ Malaga Dept Comp Architecture E-29071 Malaga Spain

In this work, we propose a new decimal redundant cordic algorithm to manage transcendental functions, using floating-point representation. The algorithms determine the direction of the elementary rotation using sign estimations. Unlike binary redundant cordic, repetition of iterations are not required to ensure convergence since novel decimal codes have been carefully selected with sufficient redundancy to prevent any repetition. The algorithms are mapped to a low-cost unit based on a decimal 3-2 carry-save adder which can also be used as a floating-point decimal division unit. Compared to current decimal floating-point units, the implementation of our algorithm involves minor modifications of the native hardware, while providing a huge set of elementary functions.

关键词： cordic algorithm decimal arithmetic carry-save arithmetic

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Design Techniques Targeting Low-Area-Power-Delay Product in Hyperbolic cordic algorithm

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COMPUTER JOURNAL 2012年第5期55卷 616-628页

作者： Aggarwal, Supriya Khare, Kavita Maulana Azad Natl Inst Technol Bhopal 462051 India

The COordinate Rotation DIgital Computer (cordic) algorithm is a famous technique for realizing complex arithmetic functions using simple shift-add operations. This paper presents a novel completely scaling-free cordic algorithm in rotation mode for high performance hyperbolic computations. We target algorithm level improvements to achieve low area and power-delay product on FPGA. Instead of complex search algorithms, we use the most significant one bit detection technique for micro-rotation sequence identification, which helps in significantly reducing the number of pipelining stages. The proposed technique uses mathematical identities to extend the range of convergence. The eight-staged pipelined architecture implementation requires a ROM in the preprocessing unit for storing the initial coordinate values, while the ROM for storing the elementary angles is eliminated. The FPGA implementation of the proposed processor requires 46.35% less gates and has 31.81% less delay when compared with Xilinx Core IP-cordic v3.0. Moreover, on an average it consumes 75.96% less power when compared with Xilinx cordic v3.0. Hence, the proposed technique provides an area-power-delay efficient VLSI implementation for calculating hyperbolic functions and exponents. The detailed algorithm design, along with FPGA implementation and area and time complexities, is presented in this paper.

关键词： cordic algorithm exponents hyperbolic functions activation functions most-significant-one Taylor series

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A scaled DCT architecture with the cordic algorithm

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IEEE TRANSACTIONS ON SIGNAL PROCESSING 2002年第1期50卷 160-167页

作者： Yu, SW Swartzlander, EE Univ Texas Dept Elect & Comp Engn Austin TX 78712 USA

This paper presents an efficient approach for computing the N-point (N = 2(n)) scaled discrete cosine transform (DCT) with the coordinate rotation digital computer (cordic) algorithm. The proposed algorithm is based on an indirect approach for computing the DCT so that the vector rotations are completely separated from the other operations and placed at the end of the DCT unit. As a result, unlike the other cordic-based DCT architectures, the proposed scaled DCT architecture does not require scale factor compensation. The number of cordic iterations is minimized through the optimal angle recoding method based on the three-value cordic algorithm. Although this three-value cordic algorithm results in different scale factors for different angles, this does not incur any extra hardware in the proposed scaled DCT architecture.

关键词： cordic algorithm discrete cosine transform scaled DCT algorithm

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Low Latency Hybrid cordic algorithm

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IEEE TRANSACTIONS ON COMPUTERS 2014年第12期63卷 3066-3078页

作者： Shukla, Rohit Ray, Kailash Chandra Univ Wisconsin Dept Elect & Comp Engn Madison WI 53706 USA Indian Inst Technol Dept Elect Engn Patna 800013 Bihar India

cordic (COordinate Rotational DIgital Computer) has gained momentum for decades because of its less hardware complexity in real time applications such as communication systems, signal and image processing. The main drawbacks of cordic algorithm are increased number of iterations, scale factor calculation and compensation. Researchers have worked to reduce the latency in terms of number of iterations and minimize the critical path with redundant arithmetic and fast adders. Some researchers have proposed algorithms to reduce the number of iterations n/2 to plus additional iterations including rotation and scale factor calculation and compensation for n bit precision. However, to the knowledge of the authors, no further reduction of number of iterations has been addressed. In this context, the authors have proposed a new hybrid cordic algorithm which reduces the iteration to (3n/8) + 1 for bit precision including the scale factor calculation and compensation. The proposed algorithm and its first order architecture have been compared with the existing low latency cordic algorithms in terms of iterations, hardware complexity and critical delay. The scope of this work is to present a novel hybrid cordic algorithm along with first order hardware architecture.

关键词： cordic algorithm radix-4 double step branching low latency hybrid cordic algorithm

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High performance rotation architectures based on the radix-4 cordic algorithm

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IEEE TRANSACTIONS ON COMPUTERS 1997年第8期46卷 855-870页

作者： Antelo, E Villalba, J Bruguera, JD Zapata, EL UNIV MALAGA DEPT ARQUITECTURA & COMPUTADORESETSI INFORMATMALAGA 29080SPAIN

Traditionally, cordic algorithms have employed radix-2 in the first n/2 microrotations (n is the precision in bits) in order to preserve a constant scale factor. In this work, we will present a full radix-4 cordic algorithm in rotation mode and circular coordinates and its corresponding selection function, and we will propose an efficient technique for the compensation of the nonconstant scare factor. Three radix-4 cordic architectures are implemented: 1) a word serial architecture based on the zero skipping technique, 2) a pipelined architecture, and 3) an application specific architecture (the angles are known beforehand). The first two are general purpose implementations where redundant(carry-save) or nonredundant arithmetic can be used, whereas the last one is a simplification of the first two. The proposed architectures present a good trade-off between latency and hardware complexity when compared with already existing cordic architectures.

关键词： cordic algorithm radix-4 redundant arithmetic VLSI architectures pipelined architectures

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Error analysis and reduction for angle calculation using the cordic algorithm

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IEEE TRANSACTIONS ON COMPUTERS 1997年第11期46卷 1264-1271页

作者： Antelo, E Bruguera, JD Lang, T Zapata, EL UNIV CALIF IRVINE DEPT ELECT & COMP ENGN IRVINE CA 92697 USA UNIV MALAGA DEPT COMP ARCHITECTURE E-29071 MALAGA SPAIN

In this paper, we consider the errors appearing in angle computations with the cordic algorithm (circular and hyperbolic coordinate systems) using fixed-point arithmetic. We include errors arising not only from the finite number of iterations and the finite width of the data path, but also from the finite number of bits of the input. We show that this last contribution is significant when both operands are small and that the error is acceptable only if an input normalization stage is included, making unsatisfactory other previous proposals to reduce the error. We propose a method based on the prescaling of the input operands and a modified cordic recurrence and show that it is a suitable alternative to the input normalization with a smaller hardware cost. This solution can also be used in pipelined architectures with redundant carry-save arithmetic.

关键词： cordic algorithm angle computation error analysis redundant arithmetic operand normalization

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Implementation of FPGA design of FFT architecture based on cordic algorithm

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INTERNATIONAL JOURNAL OF ELECTRONICS 2021年第11期108卷 1914-1939页

作者： Inguva, Sharath Chandra Seventiline, J. B. St Peters Engn Coll Dept Elect & Commun Engn Hyderabad India GITAM Deemed Be Univ Gitam Inst Technol Dept Elect Elect & Commun Engn Visakhapatnam Campus Visakhapatnam Andhra Pradesh India

The coordinate rotation digital computer (cordic) is a class of shift-add algorithm for the rotation of vectors on a plane. The major problem in this cordic algorithm is the linear rate of convergence with the speed of the iteration. The main aim of the improved cordic algorithm is to utilise an integrated adder subtractor in place of binary adder subtractor to decrease the count of iterations and hardware reduction technique. The improved cordic splits the rotation angle into several series of micro-rotation angles to calculate the rotation and the new set of angle provides a fast convergence. The canonical signed-digit (CSD) approach together with Hcub algorithm employs for the number of adder subtractor reduction and shifters in cordic architecture design. The performances of the proposed cordic design have been verified by employing it in FFT implementation. The simulation result indicates the higher frequency of 77.20%, 82.78%, 78.30% and 76.57% when compared with conventional methods. The evaluation of FFT is also done by comparing with the conventional methods. The power consumption, number of iterations and the hardware complexity reduced by using the improved cordic and the working of this proposed algorithm is evaluated through the FPGA implementation.

关键词： cordic algorithm canonical signed-digit Hcub algorithm integrated adder subtractor

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3-MU-M VLSI PROCESSING ELEMENT USING THE cordic algorithm

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ELECTRONICS LETTERS 1987年第21期23卷 1164-1166页

作者： VAUDIN, GJ NUDD, GR VLSI Architectures Group Department of Computer Science University of Warwick Coventry UK

A VLSI implementation of a unified algorithm with the capability of computing all the common arithmetic operations, including division, square rooting etc. and most trigonometric functions, is described. The processor has been designed in 3 μm CMOS technology such that when organised in a pipeline array it can achieve computation rates equivalent to 50 ns, suitable for most real-time signal and image processing applications.

关键词： image processing pipeline array common arithmetic operations cordic algorithm VLSI Digital arithmetic methods digital arithmetic square rooting real-time signal Digital signal processing VLSI implementation trigonometric functions signal processing division CMOS technology picture processing CMOS integrated circuits

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