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20th IEEE Symposium on Personal, Indoor and Mobile Radio Communications

作者： Cortez, Joaquin Bazdresch, Miguel Garcia, Armando ITSON Univ Dept Elect Engn Obregon Mexico ITSON Univ Dept Elect Engn Guadalajara Jalisco Mexico

ISBN: (纸本)9781424451234

In this work we propose a very low complexity OSIC detector based on Sorted QR decomposition (SQRD) for signal detection in hybrid STBC-VBLAST systems where the number of receive antennas is at least equal to the number of transmit layers. The proposed detector reduces the complexity by at least 50% compared with the conventional SQRD algorithm, and uses Givens Rotations implemented using cordic to calculate the QR decomposition. We show how the proposed detection scheme outperforms other recent detection schemes for STBC-VBLAST systems in terms of bit error rate and required complexity.(1)

关键词： MIMO Receivers Hybrid Space-Time Codes Givens rotations cordic algorithm

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Hardware Implementation of 3D Pipelined Laplace Filter Based on Rotation Structures 24

Hardware Implementation of 3D Pipelined Laplace Filter Based...

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24th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES)

作者： Poczekajlo, Pawel Wawryn, Krzysztof Koszalin Univ Technol Fac Elect & Comp Sci Koszalin Poland

ISBN: (纸本)9788363578121

A hardware implementation of 3D pipelined Laplace filter has been presented in the paper. The filter is composed of rotation and delay unit structures with a help of cordic algorithm. Synthesis of the pipelined 3D Laplace filter is based on synthesis of 2D and 1D filters. Proposed implementation of the filter has been compared to the implementation of the filter based on direct form. Parameters of both filter structures implemented in FPGA, have been measured and compared.

关键词： 3D FPGA Laplace filter pipelined rotation structures cordic algorithm

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Efficient FPGA-Based Implementation of a CAZAC Sequence Generator for 3GPP LTE

Efficient FPGA-Based Implementation of a CAZAC Sequence Gene...

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2014 International Conference on Reconfigurable Computing and FAGAs

作者： de Figueiredo, Felipe A. P. Mathilde, Fabiano S. Cardoso, Fabbryccio A. C. M. Vilela, Rafael M. Miranda, Joao Paulo CPqD Res & Dev Ctr DRC Convergent Networks Dept Campinas SP Brazil

ISBN: (纸本)9781479959440

This paper presents a configurable and optimized hardware architecture for computing Zadoff-Chu (ZC) complex sequences in the frequency domain. It is a hardware-efficient and accurate architecture for computing ZC sequences in real-time. The architecture is mainly based on the cordic algorithm for computing complex exponentials using only shift and add operations. Due to transformations applied to the Zadoff-Chu equation it is possible to eliminate the use of multipliers with non-constant terms. This hardware architecture is employed by the Physical Random Access Channel (PRACH) in LTE and LTE-A systems during the reception and detection of random access preambles. Its main advantage is that it eliminates the need for storing a large number of long complex ZC sequences. Simulation results show that the proposed architecture is accurate, efficient and renders the resulting PRACH receiver fully compliant with 3GPP's detection requirements.

关键词： 3G mobile communication Long Term Evolution frequency-domain analysis random sequences 3GPP LTE 3GPP detection CAZAC sequence generator cordic algorithm FPGA LTE-A systems PRACH ZC complex sequences Zadoff-Chu complex sequences complex exponentials frequency domain optimized hardware architecture physical random access channel random access preambles shift-add operations Base stations Equations Frequency-domain analysis Generators Random access memory Table lookup

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Design of a Novel Digital Phantom for EIT System Calibration

Design of a Novel Digital Phantom for EIT System Calibration

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33rd Annual International Conference of the IEEE Engineering-in-Medicine-and-Biology-Society (EMBS)

作者： Li, Nan Wang, Wei Xu, Hui Natl Univ Def Technol Sch Elect Sci & Engn Changsha 410073 Hunan Peoples R China Univ Sussex Biomed Engn Res Grp Brighton BN1 9QT E Sussex England Univ Sussex Brighton BN1 9QT E Sussex England Natl Univ Def Technol Changsha 410073 Peoples R China

ISBN: (纸本)9781424441228

This paper presented the design method of a novel digital phantom for electrical impedance tomography system calibration. By current sensing, voltage generating circuitry and digital processing algorithms implemented in FPGA, the digital phantom can simulate different impedances of tissues. The hardware of the digital phantom mainly consists of current sensing section, voltage generating section, electrodes switching section and a FPGA. Concerning software, the cordic algorithm is implemented in the FPGA to realize direct digital synthesis (DDS) technique and related algorithms. Simulation results show that the suggested system exhibits sufficient accuracy in the frequency range 10 Hz to 2 MHz. With the advantages offered by digital techniques, our approach has the potential of speed, accuracy and flexibility of the EIT system calibration process.

关键词： cordic algorithm Calibration DDS technique EIT system calibration Electrodes FPGA Field programmable gate arrays Impedance Phantoms Sensors Tomography bioelectric phenomena biological tissues biotissue impedance current sensing digital phantom design digi

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An image processing system scheme in B mode ultrasonic ophthalmological scanner 16

An image processing system scheme in B mode ultrasonic ophth...

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16th IEEE Symposium on Computer-Based Medical Systems

作者： Tan, YY Zhang, N Nanjing Univ Dept Elect Sci & Engn Nanjing 210008 Peoples R China

ISBN: (纸本)0769519016

B mode ultrasonic ophthalmological scanners are used widely in clinic diagnosing of eye diseases. Digital Scan Converter (DSC) is a key component in their image processing systems, which Performs coordinate transformation and image interpolation between two adjacent scan lines. In this paper, we present a new image processing system scheme based on the FPGA technology. In this scheme, we mainly focus on the DSC component. In the DSC system, we applied the cordic algorithm to perform the transformation between Cartesian coordinates and polar coordinates, and use a modified R-theta algorithm to perform the image interpolations. At the same time, we mapped the. whole system into a Xilinx FPGA device (XCV50-BG256). Its performance in practical application indicates that the scheme is valid and can improve the image quality significantly and greatly reduce the dimensions of this instrument.

关键词： medical image processing eye biomedical ultrasonics algorithm theory digital simulation interpolation B mode ultrasonic ophthalmological scanners eye diseases image processing systems coordinate transformation image interpolation image processing system scheme digital scan converter component digital scan converter system cordic algorithm Cartesian coordinates polar coordinates modifed R-theta algorithm performance image quality

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A 200MHz Low-Power Direct Digital Frequency Synthesizer Based on Mixed Structure of Angle Rotation

A 200MHz Low-Power Direct Digital Frequency Synthesizer Base...

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IEEE 8th International Conference on ASIC

作者： Wan Shuqin Huang Yiding Zhang Kai-hong Yu Zongguang Jiangnan Univ Sch Informat Engn Wuxi 214000 CO Peoples R China Nanyang Normal Univ Phys & Elect Engn Coll Henan 473000 Peoples R China China Elect Technol Grp Corp Wuxi 214000 Peoples R China

ISBN: (纸本)9781424438686

Direct digital frequency synthesizer(DDS) is a new technology for frequency synthesis. This paper describers the implementation of a direct digital frequency employs a new architecture in 0.35 mu m CMOS technology. The first rotation implementer by using a cordic realized in pipeline and carry-save arithmetic. The directions of the cordic rotations are computed in parallel by using a little lookup table, for the first rotation. In order to reduce the circuit latency and increase the speed, the final rotation is multiplier-based, employing CMOS-DPL logic. The final circuit experiment results show the power dissipation as low as 1.44mW/MHz and the maximum clock frequency 200 MHz(1)

关键词： Direct digital frequency synthesizer (DDFS) cordic algorithm pipeline angle rotation

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VHDL-based design and design methodology for reusable high performance direct digital frequency synthesizers

VHDL-based design and design methodology for reusable high p...

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38th Design Automation Conference (DAC)

作者： Janiszewski, I Hoppe, B Meuth, H FH Darmstadt Fachbereich Elektrotechn D-64295 Darmstadt Germany

ISBN: (纸本)1581132972

Design methodologies for high performance Direct Digital Frequency Synthesizers (DDFS) are described. Traditional look-up tables (LUT) for sine and cosine are merged with cordic-interpolation into a hybrid architecture. This implements DDFS-systems with high resolution without being specific to a particular target technology. Amplitude constants were obtained from mathematical trigonometric functions of the IEEE math - real package. These constants were then written via simulation of a VHDL model into a fully synthesizable package. Systematic and detailed studies varying the synthesizer's inherent parameters lead to a design optimum of the LUT/cordic-ratio, which minimizes power and silicon area for a given clock frequency.

关键词： cordic algorithm Design optimization and reuse Direct frequency synthesis HDL-based design

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An Efficient Pipelined Feedback Processor for Computing a 1024-Point FFT Using Distributed Logic

An Efficient Pipelined Feedback Processor for Computing a 10...

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International Conference on Computer, Communication and Computational Sciences (IC4S)

作者： Hung Ngoc Nguyen Kim, Cheol-Hong Kim, Jong-Myon Univ Ulsan Sch Elect Engn Ulsan South Korea Chonnam Natl Univ Sch Elect & Comp Engn Gwangju South Korea

ISBN: (纸本)9789811303418;9789811303401

This paper proposes an effective fast Fourier transform (FFT) processor for 1024-point computation based on the radix-2 of decimation-in-frequency (R2DIF) and uses the pipelined feedback (PF) technique via shift registers to efficiently share the same storage between the inputs and outputs during computation. The large memory footprint of the complex twiddle factor multipliers, and hence, area on a chip, of the proposed design is reduced by employing the coordinate rotation digital computer (cordic), which replaces the complex multipliers and does not require memory blocks to store the twiddle factors. To enhance the efficient usage of the hardware resources, the proposed design only uses distributed logic. This can eliminate the use of dedicated functional blocks, which are usually limited to the target chip. The entire proposed system is mapped on a Virtex-7 field-programmable gate array (FPGA) for functional verification and synthesis. The achieved result is the proposed FFT processor more effective in terms of the speed, precision, and resource, as shown in experimental results.

关键词： Radix-2 FFT Pipelined feedback cordic algorithm FPGA

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Anti-Aliasing through the Use of Coordinate Transformations

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ACM Transactions on Graphics (TOG) 1982年第3期1卷 215-234页

作者： Turkowski, K. CADLINC Inc. Palo Alto CA 94306 480 California Avenue United States

The use of the perpendicular point-line distance in evaluating the two-dimensional anti-aliasing convolution is studied. Transformations of the point-spread function (PSF) that give the effective convolution in terms of the point-line distance when the class of object space primitives is limited to lines and polygons are derived. Because the quality of filtering is embedded in a table indexed by the point-line distance, this approach allows one to use arbitrarily complex PSFs;only the width and not the shape of the PSF affects the amount of computation. The cordic algorithm is applied to point-line distance evaluation, and its merits are shown. Also shown are the more standard uses of the cordic algorithm for coordinate rotation, for polar-to-rectangular and rectangular-to-polar conversion, and for calculating the Euclidean norm of a vector. Rounded endpoints can be achieved by using the point-segment distance, and computational methods are given, including cordic implementation. The cordic algorithms for the aforementioned geometric operations are prime candidates for VLSI implementation because of their inherent parallel/pipeline nature. © 1982, ACM. All rights reserved.

关键词： anti-aliasing cordic algorithm point-line distance point-segment distance point-spread function (PSF)

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Study of S-band Antenna Tracking algorithm Based on FPGA 16

Study of S-band Antenna Tracking Algorithm Based on FPGA

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16th IEEE International Conference on Ubiquitous Wireless Broadband (ICUWB)

作者： Tan, Wen Liu, Kai Liao, Jia Nanjing Univ Sci & Technol Sch Elect & Opt Engn Nanjing 210094 Jiangsu Peoples R China Nanjing Univ Sci & Technol Microwave & Commun Engn Res Ctr Nanjing 210094 Jiangsu Peoples R China

ISBN: (纸本)9781509013173

Most conventional antenna tracking algorithm in the DSP implementation, often require a separate DSP or CPU hardware units. The aerospace applications in order to meet the miniaturization, low power requirements, based on the communication signal processing on FPGA antenna tracking algorithm, additional antenna tracking computing unit is not required. Coordinate changes and solving the beam steering angle of operation of the algorithm involved in ensuring the accuracy to meet the engineering requirements of the premise, using a look-up table, multiplier and cordic algorithm structure of pipe-line contour integration, low hardware cost method to calculate, the beam steering-angle.

关键词： antenna tracking beam steering-angle cordic algorithm

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