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作者： Kenneth Harper Kems Roger Stuart Cooper United States Naval Postgraduate School

学位级别：硕士

A special-purpose digital computer has been developed using the new ECS LSI microprocessor technology. The primary gcal of this work was to solve a fairly complicated computing task using a minimal amount of random logic and limited development time. This computing system solves ships' maneuvering board problems including the deter ruination of course, speed, and closest point of approach cf other ships. Ten contacts can be tracked simultaneously. The triangula tion involved in these calculations is performed using a decimal version cf the COREIC algorithm. A complete maneuvering situation can be computed in 4.5 seconds. Except for hardware required to drive the displays, all logic is contained in the software-encoded read-only-memory chips, which drive a single CPU chip. Approximately eight hundred man-hours were required to develop the programs and prototype the hardware. The system is modular and easy to maintain, low in bulk, power consumption, and cost.

关键词： cordic algorithm CPA (closest point of approach) LED (light-emitting diode) display maneuvering board MCS-4 Micro Computer Set microcomputer microprocessor PROM (programmable read-only-memory) RAM (random-access-memory) relative movement problem ROM (read-only-memory)

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Twiddle Factor generation using cordic Processor for Fingerprint Application

Twiddle Factor generation using CORDIC Processor for Fingerp...

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International Conference on Computer, Communication and Control

作者： Suraj N. Shinde SUK India

ISBN: (纸本)9781479981656

Fingerprint applications are widely used to identify person's authenticity. The frequency domain analysis of fingerprint plays an important role for authentication of noisy fingerprint images. This paper proposes a cordic algorithm: a unique computing technique suitable for solving trigonometric functions like sine, cosine and arctanto extract features of fingerprint image using FFT for perfect matching. The idea is to reduce the computational complexity of FFT using cordic processor. The cordic processor is hardware efficient which minimizes the computational complexity for twiddle factor computations. The FFT extract features of fingerprint and is implemented using cordic processor which consumes 390 LUTs on VIRTEX 4 FPGA.

关键词： cordic algorithm Rotation and vectoring mode Fingerprint FPGA

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Base-N Logarithm Implementation on FPGA for the Data with Random Decimal Point Positions

Base-N Logarithm Implementation on FPGA for the Data with Ra...

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IEEE 9th International Colloquium on Signal Processing and its Applications (CSPA)

作者： Liu Bangqiang He Ling Yan Xiao Univ Elect Sci & Tech China Sch Aeronaut & Astronaut Chengdu Peoples R China

ISBN: (纸本)9781467356091

Logarithmic transformation is an important part of many digital signals processing system, especially in the fields of instruments design. This paper gives details on a simple way based on cordic algorithm and the idea of data initialization to implement logarithmic transformation. Given the number of bits for input data, we can get the corresponding base-N logarithmic results after we specify their decimal point positions at will. The logarithmic converter introduced by this paper is able to support the logarithmic transformation of data with the number of bits up to 48.

关键词： Logarithm cordic algorithm decimal point positions

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FPGA-Based Resource-Optimal Approximate Multiplier for Error-Resilient Applications

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INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS 2024年第0期

作者： Khurshid, Burhan NIT Srinagar Dept ECE Srinagar J&K India

Arithmetic units inspired by approximate computations have seen a significant development in error-resilient applications, wherein accuracy can be traded off for enhanced performance. Most of the existing literature pertaining to approximate computations targets ASIC platforms. In this paper, we focus on exploiting the features of approximate computation to design efficient digital hardware for FPGA platforms. Specifically, we propose an FPGA implementation of an approximate multiplier unit based on the cordic algorithm. Contemporary FPGA-based approximate multiplier implementations report a lot of compromise in accuracy and a relatively higher implementation cost in terms of utilized resources, timing, and energy. We conduct a detailed Pareto analysis to determine the number of optimal computing stages for the proposed cordic-based approximate multiplier that justifies the accuracy-performance trade-offs. More importantly, we focus on the optimal logic distribution of the proposed multiplier circuit by restructuring the top-level Boolean network and translating it into a circuit netlist that can be efficiently mapped onto the inherent FPGA fabric of LUTs and Carry4 primitives. Our cordic-based implementations significantly improve the accuracy metrics while maintaining a suitable performance trade-off. The efficacy of our proposed multiplier is tested using two image-processing applications, namely, image blending and image smoothening. The obtained results show a substantial improvement over the existing state-of-the-art approximate multipliers.

关键词： approximate multiplier cordic algorithm error-resilient computing fixed-point arithmetic FPGA primitives

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A Universal Digital Lock-in Amplifier Design for Calibrating the Photo-Detector Responses with Standard Black-Bodies

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SENSORS 2023年第21期23卷 8902-8902页

作者： Yao, Zheyi Pan, Jingpeng Yu, Chang Yuan, Zhewen Chen, Qian Sui, Xiubao Nanjing Univ Sci & Technol Sch Elect & Opt Engn 200 Xiaolingwei Nanjing 210094 Peoples R China Jiangsu Key Lab Spectral Imaging & Intelligent Sen Nanjing 210094 Peoples R China

The lock-in amplifier (LIA) is widely utilized to detect ultra-weak optical periodic signals based on the phase-sensitive and enhanced detecting theory. In this paper, we present an all-digital and universal embedded LIA platform that accurately and conveniently describes the spectrum generated by standard black bodies at various temperatures with different optical detectors. The proposed design significantly reduces the complexity and cost of traditional analog LIAs while maintaining accuracy. The LIA components are implemented using a single field programmable gate array (FPGA), offering flexibility to modify parameters for different situations. The normalized mean-square error (NMSE) of the captured spectra in the experiments is within 0.9% compared the theoretical values.

关键词： lock-in amplification algorithm IIR filter DDS cordic algorithm

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Design and Implementation of Digital Demodulator For Frequency Modulated CW Radar

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INTERNATIONAL JOURNAL OF ENGINEERING 2014年第10期27卷 1581-1589页

作者： Mandal, A. Mishra, R. Gautam Buddha Univ Sch Informat & Commun Technol Greater Noida India

Radar Signal Processing has been an interesting area of research for realization of programmable digital signal processor using VLSI design techniques. Digital Signal Processing (DSP) algorithms have been an integral design methodology for implementation of high speed application specific real-time systems especially for high resolution radar. In recent times, cordic algorithm is turned out to be a huge researched outcome for its easy realizability in on-chip design in the field of vector rotated DSP applications. In this paper, we propose a pipelined cordic architecture for digital demodulation in high performance, low power frequency modulated CW Radar. A complex Digital Phase Locked Loop (DPLL) has been used for digital demodulation with pipelined cordic module as its core processing element. The FPGA implementation of cordic based design has been chosen because of its inherent high throughput of system due to its pipelined architecture where latency is reduced in each of the pipelined stage. Substantial amount of resource utilization has been reduced in proposed design. For better loop performance of first order complex DPLL during demodulation, the convergence of the cordic architecture is also optimized. Multiplierless BOXCAR filter has been incorporated at the final stage of the design for better information recovery from narrow samples with little energy signal and easy realization. Hardware synthesized result using Cadence design tools are presented.

关键词： FMCW Radar Digital Demodulation cordic algorithm Digital PLL BOXCAR Filter FPGA

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Field Programmable Gate Arrays Based Real Time Robot Arm Inverse Kinematic Calculations and Visual Servoing

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ELECTRICA 2018年第2期18卷 143-150页

作者： Celik, Baris Ak, Ayca Topuz, Vedat Marmara Univ Sch Engn Dept Elect Elect Engn Istanbul Turkey Marmara Univ Vocat Sch Tech Sci Istanbul Turkey

Reliability and precision are very important in space, medical, and industrial robot control applications. Recently, researchers have tried to increase the reliability and precision of the robot control implementations. High precision calculation of inverse kinematic color based object recognition, and parallel robot control based on field programmable gate arrays (FPGA) are combined in the proposed system. The precision of the inverse kinematic solution is improved using the coordinate rotation digital computer (cordic) algorithm based on double precision floating point number format. Red, green, and blue (RGB) color space is converted to hue saturation value (HSV) color space, which is more convenient for recognizing the object in different illuminations. Moreover, to realize a smooth operation of the robot arm, a parallel pulse width modulation (PWM) generator is designed. All applications are simulated, synthesized, and loaded in a single FPGA chip, so that the reliability requirement is met. The proposed method was tested with different objects, and the results prove that the proposed inverse kinematic calculations have high precision and the color based object recognition is quite successful in finding coordinates of the objects.

关键词： Video processing robot arm control inverse kinematic cordic algorithm field programmable gate arrays

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Advanced Phase Estimation and Design for Next-Generation Radar Systems: A Digital Approach

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TRAITEMENT DU SIGNAL 2024年第2期41卷 827-833页

作者： Sivaprasad, Ponduri Venkataraman, Anandi Murty, P. Satyanarayana RVR&JC Coll Engn ECE Dept Guntur 522019 Andhra Pradesh India Visvesvaraya Technol Univ Belagavi 590018 Karnataka India Ramaiah Inst Technol ECE Dept MSRIT Post Bangalore 560054 Karnataka India Gonna Inst Informat Technol & Sci Visakhapatnam 530053 Andhra Pradesh India

Recent advancements in radar technology necessitate the development of effective digital designs to enhance productivity and reliability, thereby accelerating radar-based applications. This study focuses on the integration of highly accurate phase degree estimation, taking into account the diverse wireless standards prevalent in space applications. Field-Programmable Gate Arrays (FPGAs) in the semiconductor industry, known for their adaptability and scalability, play a pivotal role in advancing space design modeling. This paper presents an analysis of various design challenges encountered in implementing radar systems, introducing a novel approach for milli-degree phase approximation coupled with hardware optimization. The research introduces an enhanced floating-point arithmetic model with double precision, specifically designed to address minute phase errors in time-variant analog signals. The system under investigation examines fundamental signals, including amplitude, frequency, and phase measurements, in relation to the developed sample blocks. High-performance phase approximation design methods proposed herein address issues associated with conventional phase detection and synchronization. To overcome performance trade-offs in traditional phase-detection designs due to signal frequency variations, a cordic-based iterative phase computing system is developed. Additionally, a phase correction mechanism is designed for precise milli-degree phase estimation. This comprehensive approach not only refines phase estimation techniques but also contributes significantly to the field of radar applications, particularly in the context of digital system design and signal processing.

关键词： radar system design Field-Programmable Gate Array (FPGA) milli-degree phase estimation cordic algorithm digital signal processing

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Improving the signal-to-noise ratio in a fiber-optic Fabry-Perot acoustic sensor

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LASER PHYSICS LETTERS 2019年第6期16卷 065106-065106页

作者： Moradi, Flamed Hosseinibalam, Fahimeh Hassanzadeh, Smaeyl Univ Isfahan Dept Phys Esfahan 81746 Iran

A fiber-optic Fabry-Perot acoustic sensor with a similar to 50 nm-thick multilayer graphene diaphragm is reported. In this paper, the results of the simulation and experimental investigation of the Fabry-Perot acoustic sensor are primarily presented, and the main area of interest is studying the different algorithms for enhancement of the sensor sensitivity. The phase generated carrier (PGC) demodulation algorithm is presented, based on differential-cross-multiplying (DCM), the arctangent (ATAN) function and ATAN based on a coordinate rotation digital computer cordic algorithm. The simulation results reveal that the PGC demodulation method, based on the ATAN cordic algorithm, has a better result (signal-to-noise ratio) than the DCM and ATAN function without using the cordic algorithm. On this account, a PGC demodulation algorithm based on the ATAN method with a cordic algorithm is applied in the experimental investigation due to the simulation results and simpler digital implementation on a field programmable gate array. The acoustic sensor shows a high frequency response from 8-10 kHz and may be useful for highly sensitive acoustic sensing without temperature and pressure fluctuation. The results also show acoustic sensitivity in the order of -98 dB re rad mu Pa-1 at 1 kHz.

关键词： acoustic sensing Fabry-Perot graphene cordic algorithm optical fiber sensor

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The method on improving digital decoding accuracy of the resolver 6

The method on improving digital decoding accuracy of the res...

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6th International Conference on Instrumentation and Measurement, Computer, Communication and Control (IMCCC)

作者： Yang Ruifeng Guo Chenxia Zhang Peng Yang Ruifeng Guo Chenxia Zhang Peng North Univ China Sch Instrument & Elect Taiyuan Peoples R China Automat Test Equipment & Syst Engn Res Ctr Shanxi Taiyuan Peoples R China

ISBN: (纸本)9781509011957

The discarded non-zero bit in multiple shift operations of cordic algorithm using the micro-controllers to decode the resolver angle will reduce the decoding accuracy of resolver. The compensation algorithm was proposed to improve the decoding accuracy in the paper. Results demonstrate that the proposed compensation algorithm can improve the decoding accuracy effectively using cordic algorithm in micro-controller system.

关键词： the resolver angle decoding cordic algorithm decoding accuracy

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