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16th IEEE Symposium on Computer-Based Medical Systems

作者： Tan, YY Zhang, N Nanjing Univ Dept Elect Sci & Engn Nanjing 210008 Peoples R China

ISBN: (纸本)0769519016

B mode ultrasonic ophthalmological scanners are used widely in clinic diagnosing of eye diseases. Digital Scan Converter (DSC) is a key component in their image processing systems, which Performs coordinate transformation and image interpolation between two adjacent scan lines. In this paper, we present a new image processing system scheme based on the FPGA technology. In this scheme, we mainly focus on the DSC component. In the DSC system, we applied the cordic algorithm to perform the transformation between Cartesian coordinates and polar coordinates, and use a modified R-theta algorithm to perform the image interpolations. At the same time, we mapped the. whole system into a Xilinx FPGA device (XCV50-BG256). Its performance in practical application indicates that the scheme is valid and can improve the image quality significantly and greatly reduce the dimensions of this instrument.

关键词： medical image processing eye biomedical ultrasonics algorithm theory digital simulation interpolation B mode ultrasonic ophthalmological scanners eye diseases image processing systems coordinate transformation image interpolation image processing system scheme digital scan converter component digital scan converter system cordic algorithm Cartesian coordinates polar coordinates modifed R-theta algorithm performance image quality

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cordic algorithm for vectoring mode without constant scaling factors

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ELECTRONICS LETTERS 1999年第12期35卷 971-972页

作者： Juang, TB Lin, HF Ta Jen Jr Coll Pharm Dept Hlth Adm Ping Tung Cty Taiwan Feng Chia Univ Dept Informat Engn Taichung 40724 Taiwan

A new cordic algorithm is presented that can be used for the vectoring mode without requiring constant scaling Factors. The algorithm can also be used to carry out complete transformation from rectangular co-ordinates (x, y) to polar co-ordinates (rho,theta). In each iteration, the exponent difference of x and y is computed so as to speed up convergence. This new cordic algorithm has an average of 0.75 n iterations for n-bit input data and can achieve > 94.78% 23 bit accuracy. It is also suitable for VLSI chip implementation due to the regular architecture required.

关键词： convergence Digital arithmetic methods digital arithmetic iteration co-ordinate transformation VLSI chip cordic algorithm vectoring mode

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Optimisation of direct digital frequency synthesisers based on cordic

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ELECTRONICS LETTERS 2001年第21期37卷 1278-1280页

作者： Cardells-Tormo, F Valls-Coquillat, J Univ Politecn Valencia Dept Elect Engn E-46071 Valencia Spain Univ Politecn Valencia Dept Elect Engn EPSG Grao De Gandia 46730 Spain

Methods to simplify digital frequency synthesisers based on the co-ordinate rotation digital computer (cordic) algorithm are presented. Application of the-se methods leads to performance enhancement, compared with the topologies previously proposed in the literature. For a given output precision, hardware resources are reduced and spur-free dynamic range is increased.

关键词： optimisation direct digital frequency synthesiser spur-free dynamic range circuit topology Signal generators Optimisation techniques Other digital circuits circuit optimisation cordic algorithm signal processing direct digital synthesis

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VHDL-based design and design methodology for reusable high performance direct digital frequency synthesizers

VHDL-based design and design methodology for reusable high p...

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38th Design Automation Conference (DAC)

作者： Janiszewski, I Hoppe, B Meuth, H FH Darmstadt Fachbereich Elektrotechn D-64295 Darmstadt Germany

ISBN: (纸本)1581132972

Design methodologies for high performance Direct Digital Frequency Synthesizers (DDFS) are described. Traditional look-up tables (LUT) for sine and cosine are merged with cordic-interpolation into a hybrid architecture. This implements DDFS-systems with high resolution without being specific to a particular target technology. Amplitude constants were obtained from mathematical trigonometric functions of the IEEE math - real package. These constants were then written via simulation of a VHDL model into a fully synthesizable package. Systematic and detailed studies varying the synthesizer's inherent parameters lead to a design optimum of the LUT/cordic-ratio, which minimizes power and silicon area for a given clock frequency.

关键词： cordic algorithm Design optimization and reuse Direct frequency synthesis HDL-based design

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VHDL-based design and design methodology for reusable high performance direct digital requency synthesizers 01

VHDL-based design and design methodology for reusable high p...

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Proceedings of the 38th annual Design Automation Conference

作者： Ireneusz Janiszewski Bernhard Hoppe Hermann Meuth FH Darmstadt Fachbereich Elektrotechnik Schöfferstr. 3 D-64295 Darmstadt

ISBN: (纸本)9781581132977

Design methodologies for high performance Direct Digital Fre-quen--cy Synthesizers (DDFS) are described. Traditional look-up tab-les (LUT) for sine and co-sine are merged with cordic-inter-po---la--tion into a hybrid architecture. This implements DDFS-sys-tems with high resolution without being specific to a particular tar-get technology. Amplitude constants were obtained from ma-the-matical trigonometric functions of the IEEE math_real pack-age. These constants were then written via simulation of a VHDL model into a fully synthesizable package. Systematic and detailed studies varying the synthesizers inherent parameters lead to a design optimum of the LUT/cordic-ra-tio, which mini-mizes power and silicon area for a given clock frequency.

关键词： cordic algorithm

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Improvement of cordic algorithm

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Journal of Beijing Institute of Technology 1998年第4期7卷 400-405页

作者：石晶林李滔于波张群英韩月秋北京理工大学电子工程系北京100081

Aim To discuss the basic cordic algorithm that can be applied to digital signal processing and its applying condition called convergence *** In addition to the original basic equation, another group iterative equation was used to evaluate the correspondent values of input data that did not lie within the convergence range. Results and Conclusion The improved cordic algorithm removes the limits of the range of convergence and can adapt itself to the variations of input values. The correctness of improved cordic algorithms has been proved by calculating examples.

关键词： convergence, iterative equation cordic algorithm

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A multicarrier QAM modulator

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2000年第1期47卷 1-10页

作者： Vankka, J Kosunen, M Sanchis, I Halonen, KAI Aalto Univ Elect Circuit Design Lab FIN-02015 Espoo Finland

A multicarrier quadrature amplitude modulation (QAM) modulator has been developed and implemented with programmable logic devices. The multicarrier QAM modulator contains four cordic-based QAM modulators. A conventional QAM modulator needs two multipliers, one adder, and sine/cosine ROM's, The designed cordic-based QAM modulator has about the same logic complexity as the two multipliers and the adder with the same word sizes, Each QAM modulator accepts 13-bit in-phase and quadrature data streams, interpolates them by 16, and upconverts the baseband signal to a selected center frequency. The frequencies of the four carriers can be independently adjusted. The proposed multicarrier QAM modulator does not use an analog I/Q modulator, and therefore, the difficulties of adjusting the de offset, phasing, and the amplitude levels between the in-phase and quadrature-phase signal paths are avoided. The multicarrier QAM modulator is designed to fulfill the spectrum and error vector magnitude (EVM) specifications of the wideband code-division multiple-access (WCDMA) system. The simulated EVM is 1.06% root mean square (rms), well below the specified 12.5% rms for WCDMA, The measured ratio of the integrated first/second /third adjacent channel power (4.096-MHz bandwidth) to the integrated channel power (4.096-MHz bandwidth) is -68.16/-68.24/-66.17 dB versus the specified -45/-55/-55 dB.

关键词： cordic algorithm multicarrier programmable logic devices quadrature amplitude modulation wideband code-division multiple access

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High performance rotation architectures based on the radix-4 cordic algorithm

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IEEE TRANSACTIONS ON COMPUTERS 1997年第8期46卷 855-870页

作者： Antelo, E Villalba, J Bruguera, JD Zapata, EL UNIV MALAGA DEPT ARQUITECTURA & COMPUTADORESETSI INFORMATMALAGA 29080SPAIN

Traditionally, cordic algorithms have employed radix-2 in the first n/2 microrotations (n is the precision in bits) in order to preserve a constant scale factor. In this work, we will present a full radix-4 cordic algorithm in rotation mode and circular coordinates and its corresponding selection function, and we will propose an efficient technique for the compensation of the nonconstant scare factor. Three radix-4 cordic architectures are implemented: 1) a word serial architecture based on the zero skipping technique, 2) a pipelined architecture, and 3) an application specific architecture (the angles are known beforehand). The first two are general purpose implementations where redundant(carry-save) or nonredundant arithmetic can be used, whereas the last one is a simplification of the first two. The proposed architectures present a good trade-off between latency and hardware complexity when compared with already existing cordic architectures.

关键词： cordic algorithm radix-4 redundant arithmetic VLSI architectures pipelined architectures

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Error analysis and reduction for angle calculation using the cordic algorithm

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IEEE TRANSACTIONS ON COMPUTERS 1997年第11期46卷 1264-1271页

作者： Antelo, E Bruguera, JD Lang, T Zapata, EL UNIV CALIF IRVINE DEPT ELECT & COMP ENGN IRVINE CA 92697 USA UNIV MALAGA DEPT COMP ARCHITECTURE E-29071 MALAGA SPAIN

In this paper, we consider the errors appearing in angle computations with the cordic algorithm (circular and hyperbolic coordinate systems) using fixed-point arithmetic. We include errors arising not only from the finite number of iterations and the finite width of the data path, but also from the finite number of bits of the input. We show that this last contribution is significant when both operands are small and that the error is acceptable only if an input normalization stage is included, making unsatisfactory other previous proposals to reduce the error. We propose a method based on the prescaling of the input operands and a modified cordic recurrence and show that it is a suitable alternative to the input normalization with a smaller hardware cost. This solution can also be used in pipelined architectures with redundant carry-save arithmetic.

关键词： cordic algorithm angle computation error analysis redundant arithmetic operand normalization

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Fast implementation of direct robot kinematics with cordic systolic arrays

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INTERNATIONAL JOURNAL OF COMPUTER MATHEMATICS 1998年第3-4期67卷 239-260页

作者： Mertzios, BG Democritus Univ Thrace Dept Elect & Comp Engn Automat Control Syst Lab GR-67100 Xanthi Greece

This paper deals with fast implementation of the direct kinematics equations of robotic manipulators, using systolic arrays that incorporate one cordic rotor in their processing elements. The rotation or the translation motions of che links are implemented by using a processing element of general form. The processing elements used for the revolute joints incorporate one cordic rotor and at most an adder and one inverter. The processing elements used for the prismatic joints incorporate at most two adders and one inverter. The overall systolic architecture is derived by cascading the processing elements that correspond to the successive links and pipelining the unidirectional linear array. The use of systolic arrays with cordic processors results into fast pipelined VLSI architectures, which may be used as peripheral devices to a host digital computer and are suitable for computation of the kinematic equations, in run-time operation.

关键词： systolic arrays cordic algorithm pipelining robot kinematics

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