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检索条件"主题词=Cordic algorithm"

共 147 条记录，以下是21-30 订阅

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Efficient Low-Precision cordic algorithm for Hardware Implementation of Artificial Neural Network 23rd

Efficient Low-Precision CORDIC Algorithm for Hardware Implem...

引用

23rd International Symposium on VLSI Design and Test

作者： Raut, Gopal Bhartiy, Vishal Rajput, Gunjan Khan, Sajid Beohar, Ankur Vishvakarma, Santosh Kumar Indian Inst Technol Indore VLSI Circuit & Syst Design Lab Nanoscale Devices Discipline Elect Engn Indore 453552 Madhya Pradesh India

ISBN: (纸本)9789813297661;9789813297678

An efficient FPGA or ASIC based hardware implementation of deep neural networks face the challenge of limited chip area, and therefore an area efficient architecture is required to fully harness the capacity of parallel processing of FPGA and ASIC in contrast to general purpose processors. In literature, the challenges are to investigate a generalized mathematical model and architecture for neuron block in an ANN implementation. We have proposed a generalized architecture for neuron implementation based on the shift-and-add algorithm, collectively known as Coordinate Rotation Digital Computer (cordic) algorithm, having a wide range of application. The look-up-table (LUT) based approach with a shift-and-add algorithm is an alternative technique for polynomial approximation and implementation. Paper explains how the cordic algorithm works and investigates the power and area efficient versatile computational unit for ANN application. The derived model proves that for the hyperbolic tangent function required a double pseudo-rotation and additional subtraction compares to the sigmoid function. In this reference versatile approach based optimized sigmoid activation function is implemented. The function is synthesized and validate on Xilinx zynq XC7Z010clg400 SoC and result reveals the minimum resources utilization.

关键词： Artificial neural networks ASIC/FPGA hardware Shift-and-add algorithm cordic algorithm Activation function

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Area Efficient VLSI design for image processing using the modified cordic algorithm 3

Area Efficient VLSI design for image processing using the mo...

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3rd IEEE International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA)

作者： Anil, Roshan Sampath, Puppala Pavan Venkata Adi Kumar, P. Sathish Amrita Vishwa Vidyapeetham Amrita Sch Engn Dept Elect & Commun Engn Bangalore Karnataka India

ISBN: (纸本)9781665455466

The Coordinate Rotation Digital Computer (cordic) is an unsophisticated and highly efficient algorithm developed for fast and real time digital solution and performing trigonometric, hyperbolic, logarithmic and more mathematical operations, including square-root, real-complex multiplications, division, and many others which are then translated using a simple adder, subtractor, and shift operators. Although the algorithm's biggest drawback, the total number of vector rotation rounds is attempted to be reduced in this article. The hardware complexity is also being reduced which leads to silicon area reduction. Which is then implemented on an FPGA using Verilog programming language.

关键词： cordic algorithm FPGA (Field programmable gate array) VLSI Architecture

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Implementation of DCT using variable iterations cordic algorithm on FPGA 1

Implementation of DCT using variable iterations CORDIC algor...

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First International Conference on Computational Systems and Communications (ICCSC)

作者： Mane, Mansi Patil, Dhanshree Sutaone, Mukul S. Sadalage, Akshay Coll Engn Pune Dept Elect & Telecommun Pune Maharashtra India

ISBN: (纸本)9781479960132

cordic or CO-ordinate Rotation DIgital Computer is a fast, simple, coherent and powerful algorithm which is used for diversified Digital Signal Processing applications. In pursuance of speed and accuracy requirements of todays applications, we put forward variable iterations cordic algorithm. In this algorithm, to boost speed we can lessen number of iterations in cordic algorithm for specific accuracy. This enhances efficiency of conventional cordic algorithm which we have used to compute Discrete Cosine Transform for image processing. One Dimensional Discrete Cosine Transform is implemented by using only 6 cordic blocks which needs only 6 multipliers. Because of the simplicity in hardware speed of image processing on FPGA is raised. Further increase in speed can be achieved by concurrently processing number of macro-blocks of an image on FPGA.

关键词： DCT cordic algorithm FPGA

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Implementation of cordic algorithm on FPGA Altera Cyclone

Implementation of CORDIC Algorithm on FPGA Altera Cyclone

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20th Telecommunications Forum

作者： Ristovic, Milica Lubura, Slobodan Jokic, Dejan Univ East Sarajevo Fac Elect Engn East Sarajevo 71123 Bosnia & Herceg

ISBN: (纸本)9781467329842;9781467329835

In paper is presented HDL Code generation of cordic algorithm in MATLAB/Simulink, using HDL Code generation tool, and its implementation on FPGA Altera Cyclone, using Altera Quartus II. There are also tested data types which cordic uses, as well as time which is need for sine or cosine calculation of given angle, depending on these data types. With this information cordic can be easily implemented in any digital system.

关键词： Simulink HDL Coder cordic algorithm FPGA

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An Efficient High-Speed cordic algorithm Using Parallel-Prefix Adders (PPA)

An Efficient High-Speed CORDIC Algorithm Using Parallel-Pref...

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International Conference on VLSI, Communications, and Signal Processing (VCAS)

作者： Venkatesh, Vutukuri Yeswanth, Balaji Akhil, Repala Jatoth, Ravi Kumar Natl Inst Technol Dept ECE Tadepalligudem Andhra Pradesh India Natl Inst Technol Dept ECE Warangal Telangana India

ISBN: (纸本)9789813297753;9789813297746

Delay and Area ceases the actual potential of the modern gadgets. Although, human has sophisticated devices around him yet yearns to save time and space. So, this paper centers on the highly efficient cordic algorithm, known for its low-cost implementation in DSP algorithms. In an effort, to improve the algorithm further in terms of area and speed, comparative analysis has been done by replacing Ripple carry adder with Parallel-Prefix adders, namely, Brent-Kung adder, Han-Carlson adder and Kogge-Stone Adder. The algorithm was designed in VHDL using XILINX ISE 14.7 design suite and implemented in XILINX Spartan 6e FPGA. Obviously, Parallel-Prefix adders have shown improved performance.

关键词： cordic algorithm Ripple carry adder Carry look ahead adder Kogge-Stone adder Brent-Kung adder Han-Carlson adder

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FPGA Implementation of Fast and Area Efficient cordic algorithm

FPGA Implementation of Fast and Area Efficient CORDIC algori...

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International Conference on Communication and Network Technologies (ICCNT)

作者： Chinnathambi, M. Bharanidharan, N. Rajaram, S. Thiagarajar Coll Engn Dept Elect & Commun Madurai Tamil Nadu India

ISBN: (纸本)9781479962662

This paper presents the fast and area efficient cordic (Coordinate Rotation DIgital Computer) algorithm for sine and cosine wave generation. The concepts of pipelining and multiplexer based cordic algorithm is used todecrease the critical path delay and reducing the area respectively. A six stage cordic is implemented by two schemes followed by four methods, unrolled cordic and multiplexer based cordic with and without pipelining. The pipelining is included in four stages(excluding first and last stage). An 8-bit cordic algorithm for generating sine wave and cosine wave is designed, implementedand compared by all four methods on Xilinx Spartan3E (XC3S250E).

关键词： cordic algorithm FPGA Multiplexer Pipelining Unrolled cordic Sine/Cosine

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High-Speed Single Precision Floating Point Multiplier using cordic algorithm 3

High-Speed Single Precision Floating Point Multiplier using ...

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3rd International Conference on Electrical, Electronics, Communication, Computer Technologies and Optimization Techniques (IGEECCOT)

作者： Yeshwanth, Balaji Venkatesh, Vutukuri Akhil, Repala Natl Inst Technol Dept Elect & Commun Engn Tadepalligudem Andhra Pradesh India

ISBN: (纸本)9781538651308

Floating point arithmetic has paramount necessity in computer systems. Floating point multiplier is appreciably used in numerous applications which yearn for speed. Generally, floating point multiplier requires 23X23 mantissa multiplication and 8-bit exponent addition. Thus, delay of the mantissa multiplication plays a crucial role in boosting the speed. In this paper, the prime proposal is to increase the speed of the single precision floating point multiplier by implementing mantissa multiplication using cordic algorithm and exponent addition using Kogge-Stone adder which results in increasing the speed by several folds. Further, the performance of floating point multiplier using cordic algorithm and VEDIC multiplier is contemplated in terms of area, delay and power. Floating point multiplier was designed in VHDL using XILINX ISE 14.7 and implemented in XILINX Spartan 6e board. The proposed idea has shown better performance in terms of speed.

关键词： cordic algorithm Kogge-Stone adder Parallel Prefixadder Vedic multiplier Single precision floating point multiplier

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ASIC Implementation of Fixed-Point Iterative, Parallel, and Pipeline cordic algorithm 8th

ASIC Implementation of Fixed-Point Iterative, Parallel, and ...

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8th International Conference on Soft Computing for Problem Solving (SocProS)

作者： Jyothi, Grande Naga Debanjan, Kundu Anusha, Gorantla VIT Univ Vellore Tamil Nadu India GCT Coimbatore Coimbatore Tamil Nadu India

ISBN: (纸本)9789811500350;9789811500343

In this paper, we proposed a Coordinate Rotation Digital Computer (cordic) algorithm for efficient hardware implementation of mathematical functions which can be carried out in a wide variety of ways for many digital signal processing applications. The cordic is a single unified algorithm for calculating many elementary functions such as trigonometric, hyperbolic, logarithmic function, exponential functions, multiplication, division, and so on. In this paper, a novel low power, low area, and high throughput fixed-point cordic algorithms are proposed. The standard cordic is also implemented for comparing the synthesis results. The proposed architecture scaling has been done using low area and low-power Scale Factor Correction Unit (SFCU). A low ADP SQRT-CSLA based ADD/SUB unit is proposed to overcomed the disadvantages of the basic ADD/SUB unit used in the standard cordic. The ROM lookup table size is also reduced to half. Extensive simulations are performed to verify the functionality. The standard and proposed cordic architectures are simulated in cadence NC launch and synthesized in cadence RC tool using TSMC GPDK 45 nm technology and area, power, and delay are calculated. The area and power consumption of the proposed cordic architecture are less when compared with standard cordic design.

关键词： cordic algorithm Pipeline Parallel Digital signal processing

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Performance of the cordic algorithm in I-Q modulators

Performance of the cordic algorithm in I-Q modulators

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6th IASTED International Conference on Communication Systems and Networks

作者： Benavente-Peces, Cesar Pardo-Martin, Jose M. Ortega-Gozalez, Francisco J. Univ Politecn Madrid EUIT Telecommun Dept Ingn Circuitos & Sistemas Ctra Valencia Km 7 Madrid 28031 Spain

ISBN: (纸本)9780889866959

This paper analyses the use of the cordic algorithm in I-Q modulators. The analyse highlights the computational advantages of using this algorithm and the drawbacks, focusing on the fixed point arithmetic problem. Two approaches are presented and their performance is discussed based on the frequency error met by each one. Along the discussion, comparison with other computationally efficient algorithms is presented.

关键词： I-Q modulator/demodulator cordic algorithm phase rotator

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Modified cordic algorithm for Givens Rotator 24th

Modified CORDIC Algorithm for Givens Rotator

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24th International Conference on Computational Science (ICCS)

作者： Poczekajlo, Pawel Moroz, Leonid Deelman, Ewa Gepner, Pawel Univ Southern Calif USC Informat Sci Inst Marina Del Rey CA 90292 USA Koszalin Univ Technol Fac Elect & Comp Sci Koszalin Poland Warsaw Univ Technol Fac Mech & Ind Engn Warsaw Poland

ISBN: (纸本)9783031637773;9783031637780

The article presents a modified cordic algorithm for implementing a Givens rotator. The cordic algorithm is an iterative method for computing trigonometric functions and rotating vectors without using complex calculations. The authors propose two modifications for improving the classical cordic algorithm: completing iterations with one-directional rotation of the vector at the final stages and choosing a scaling factor value that can be implemented with low-cost dedicated hardware utilising canonical signed digits representation. The modified algorithm is implemented in a pipeline approach using Verilog language in an Altera Cyclone V System-on-Chip FPGA. The results show that the proposed algorithm achieves higher accuracy and lower latency than the classic cordic algorithm.

关键词： cordic algorithm Givens rotator FPGA

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