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FPGA realisation of inverse kinematics for biped robot based on cordic

ELECTRONICS LETTERS 2013年第5期49卷 332-333页

作者： Wong, C. C. Liu, C. C. Tamkang Univ Dept Elect Engn New Taipei City 25137 Taiwan

A FPGA realisation structure based on cordic is proposed to implement inverse kinematics for a biped robot. First, the angle equations of inverse kinematics for the biped robot are described. Based on these equations represented by the inverse tangent function, a FPGA structure based on two cordic operators of circular vectoring and hyperbolic vectoring is proposed and implemented on a FPGA chip. Finally, comparison of the proposed FPGA realisation and the software realisation to calculate these angle equations is presented to illustrate the effectiveness of the proposed structure.

关键词： ROBOTS COMPUTER software ENERGY consumption FIELD programmable gate arrays cordic algorithm KINEMATICS

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DESIGN OF A PIPELINED RADIX-4 cordic PROCESSOR

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PARALLEL COMPUTING 1993年第7期19卷 729-744页

作者： BRUGUERA, JD ANTELO, E ZAPATA, EL UNIV MALAGA FAC INFORMATDEPT ARQUITECTURAE-29013 MALAGASPAIN

In this work we develop a generalization of the cordic algorithm for any radix in three coordinate systems, linear, circular and hyperbolic. We carry out a comparative study between different radixes at the number of additions level, due to the fact that the complexity in additions determines the total hardware associated with the implementation of the algorithm. Radix 4 minimizes the number of additions, therefore we propose a high speed cordic processor based on this radix 4. We have developed new criteria for the vectorization and rotation modes and we introduce a new technique for the compensation of a non-constant scale factor, multifactor compensation. The processor we propose is of a general and pipelined character and uses redundant arithmetic (signed digit) in order to reduce the delay in each stage, parallelizing the operation of the adders using a competititive implementation (reduction of the number of stages) with respect to radix 2 implementations which have recently appeared in the literature.

关键词： DIGITAL SIGNAL PROCESSING cordic algorithm REDUNDANT ARITHMETIC SIGNED-DIGIT ADDERS PIPELINING

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Hardware Chip Performance of cordic Based OFDM Transceiver for Wireless Communication

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Computer Systems Science & Engineering 2022年第2期40卷 645-659页

作者： Amit Kumar Adesh Kumar Geetam Singh Tomar Faculty of Technology Uttarakhand Technical UniversityDehradun248007India Department of Electrical&Electronics Engineering School of EngineeringUniversity of Petroleum and Energy StudiesDehradun248007India Birla Institute of Applied Sciences Nainital263136India

The fourth-generation(4G)and fifth-generation(5G)wireless communication systems use the orthogonal frequency division multiplexing(OFDM)modulation techniques and subcarrier *** OFDM modulator and demodulator have inverse fast Fourier transform(IFFT)and fast Fourier transform(FFT)*** biggest challenge in IFFT/FFT processor is the computation of imaginary and real *** has been proved one of the best rotation algorithms for logarithmic,trigonometric,and complex *** proposed work focuses on the OFDM transceiver hardware chip implementation,in which 8-point to 1024-point IFFT and FFT are used to compute the operations in transmitter and receiver *** coordinate rotation digital computer(cordic)algorithm has read-only memory(ROM)-based architecture to store FFT twiddle factors and their angle *** address generation unit is required to fetch the data and write the results into the memory in the appropriate *** provides low memory,delay,and optimized hardware on the field-programmable gate array(FPGA)in comparison to normal FFT architecture for the OFDM *** comparative performance of the FFT and cordicFFT based OFDM transceiver chip is estimated using FPGA parameters:slices,flip-flops,lookup table(LUTs),frequency,power,and *** design is developed using integrated synthesis environment(ISE)Xilinx version 14.7 software,synthesized using very-high-speed integrated circuit hardware description language(VHDL),and tested on Virtex-5 FPGA.

关键词： 5G Communication cordic algorithm FFT Virtex-5 FPGA OFDM Communication

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A 380 MHz direct digital synthesizer/mixer with hybrid cordic architecture in 0.25 μm CMOS

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2007年第1期42卷 151-160页

作者： De Caro, Davide Petra, Nicola Maria Strollo, Antonio Giuseppe Univ Naples Federico II Dept Elect & Telecommun Engn I-80125 Naples Italy

The paper describes the implementation of a 380 MHz, 13 bit, direct digital synthesizer/mixer IC in 0.25 mu m CMOS technology. The circuit employs an innovative architecture which divides the pi/4 rotation operation required in the quadrature synthesizer/mixers, in three rotations. The first two rotations are implemented by using a cordic datapath completely realized in carry-save arithmetic. The directions of the cordic rotations are computed in parallel by using a little lookup table, for the first rotation, and a multiply by constant and addition circuit for the second rotation. The final (third) rotation is multiplier-based, in order to reduce the circuit latency and increase the circuit performances. The cordic datapath is implemented with a novel approach both at the algorithmic level and at the transistor level. At the algorithmic level the combined employ of sign-extension prevention, overflow prevention and a novel rounding scheme are presented. At the transistor level a design style that jointly uses full-CMOS and DPL to improve the circuit latency is described. The overall circuit performances are very interesting. The synthesizer/mixer IC, realized in a 0.25 mu m CMOS technology, has an area occupation of 0.22 mm(2) and dissipates 152 mW at 380 MHz with a supply voltage of 2.5 V.

关键词： angle rotator carry save arithmetic cordic algorithm digital downconverter direct digital frequency synthesizer digital mixer digital synthesizer digital tuner digital upconverter mixer modulator overflow prevention quadrature modulator rounding

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Virtually scaling-free adaptive cordic rotator

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IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES 2004年第6期151卷 448-456页

作者： Maharatna, K Troya, A Banerjee, S Grass, E Univ Bristol Dept Elect & Elect Engn Bristol Avon England Inst High Performance Microelect D-15236 Frankfurt Germany Indian Inst Technol Dept Elect & Elect Commun Engn Kharagpur 721302 W Bengal India

The authors propose a coordinate rotation digital computer (cordic) rotator algorithm that eliminates the problems of scale factor compensation and limited range of convergence associated with the classical cordic algorithm. In the proposed scheme, depending on the target angle or the initial coordinate of the vector, a scaling by 1 or 1/root2 is needed that can be realised with minimal hardware. The proposed cordic rotator adaptively selects the appropriate iteration steps and converges to the final result by executing on average only 50% of the number of iterations required by the classical cordic. Unlike for the classical cordic, the value of the scale factor is completely independent of the number of executed iterations. Based on the proposed algorithm, a 16-bit pipelined cordic rotator was implemented. The silicon area of the fabricated pipelined cordic rotator core is 2.73 mm(2). This is equivalent to 38 000 inverter gates in the used 0.25 mum BiCMOS technology. The average dynamic power consumption of the fabricated cordic rotator is 17 mW at a 2.5 V supply voltage and a 20 Ms/s throughput. Currently, this cordic rotator is used as a part of the baseband processor for a project that aims to design a single-chip wireless modem compliant with the IEEE 802.11a standard.

关键词： COMPUTERS cordic algorithm COMPUTER algorithms DATA transmission systems DIGITAL communications ELECTRONIC data processing ELECTRONIC systems

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Performance Realization of cordic based GMSK System with FPGA Prototyping

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INTERNATIONAL JOURNAL OF ADVANCED COMPUTER SCIENCE AND APPLICATIONS 2020年第1期11卷 577-584页

作者： Kajur, Renuka Prasad, K., V PESIT Dept Elect & Commun Engn Bengaluru India BIT Dept Elect & Commun Engn Bengaluru India

The Gaussian Minimum Shift Keying (GMSK) modulation is a digital modulation scheme using frequency shift keying with no phase discontinuities, and it provides higher spectral efficiency in radio communication systems. In this article, the cost-effective hardware architecture of the GMSK system is designed using pipelined cordic and optimized cordic models. The GMSK systems mainly consist of the NRZ encoder, Integrator, Gaussian filter followed by FM Modulator using cordic models and Digital Frequency Synthesizer (DFS) for IQ Modulation in transmitter section along with channel, the receiver section has FM demodulator, followed by Differentiator and NRZ decoder. Thecordic algorithms play a crucial role in GMSK systems for IQ generation and improve the system performance on a single chip. Both the pipelined cordic and optimized cordic models are designed for 6-stages. The optimized cordic model is designed using quadrature mapping method along with pipeline structure. The GMSK systems are implemented on Artix-7 FPGA with FPGA prototyping. The Performance analysis is represented in terms of hardware constraints like area, time and power. These results show that the optimized cordic based GMSK system is a better option than the pipelined cordic based GMSK systems for real-time scenarios.

关键词： GMSK cordic algorithm FPGA DFS Gaussian Filter pipelined integrator differentiator channel

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Optimization of cordic cells in the backward circular rotation mode

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AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS 2007年第5期61卷 337-340页

作者： Granado, J. Torralba, A. Chavez, J. Baena-Lecuyer, V. Univ Seville Escuela Super Ingn Sevilla Dept Ingn Elect Seville 41092 Spain

The COordinate Rotation DIgital Computer (cordic) algorithm in the backward circular rotation mode efficiently computes phase estimation. In this letter, a set of new rules are proposed to design a cordic processor to achieve a given signal-to-noise ratio (SNR). To this end, two new approximate expressions to estimate the SNR are derived accounting for the approximation and quantization errors, respectively. (C) 2006 Elsevier GmbH. All rights reserved.

关键词： cordic algorithm digital signal processing circuit design

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Adaptive cordic: Using Parallel Angle Recoding to Accelerate Rotations

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IEEE TRANSACTIONS ON COMPUTERS 2010年第4期59卷 522-531页

作者： Rodrigues, Terence K. Swartzlander, Earl E., Jr. Univ Texas Austin Dept Elect & Comp Engn Austin TX 78712 USA

The cordic algorithm is used in the evaluation of a wide variety of elementary functions. It is a simple and elegant method, but it suffers from long latency. The Angle Recoding method is able to reduce the number of iterations by more than 50 percent, but its implementation in hardware requires a large increase in cycle time, to accommodate its complex angle selection function. This restricts its use to those cases where the angle of rotation is fixed and known in advance, so that the angle selection can be performed offline. This paper presents a simpler implementation of the angle selection scheme that does not require an increase in cycle time, thus allowing the Angle Recoding method to be used dynamically for arbitrary angles. The method also has the advantage that all the angle constants are found in parallel, in a single step, by testing only the initial rotation angle, without having to perform successive cordic iterations. This dynamic Angle Recoding method can be formulated to use "sections," to limit the number of range comparators needed, to a reasonable value. There is an increase in the number of adaptive cordic iterations needed, but this problem can be mitigated by using a buffer in conjunction with the method of sections.

关键词： cordic algorithm angle rotation sine computation cosine computation

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HOUGH TRANSFORM USING cordic METHOD

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ELECTRONICS LETTERS 1989年第3期25卷 205-206页

作者： TIMMERMANN, D HAHN, H HOSTICKA, BJ FRAUNHOFER INST MICROELECTR CIRCUITS & SYST D-4100 DUISBURG 1FED REP GER

The purpose of the letter is to demonstrate the usefulness of the cordic algorithm for implementation of image processing algorithms in dedicated hardware to achieve near real-time processing speed. The cordic algorithm will be discussed, and also its application for line and circle detection as well as for arbitrary shapes using Hough transforms.

关键词： cordic algorithm cordic method Hough transforms arbitrary shapes circle detection computerised pattern recognition computerised picture processing dedicated hardware image processing algorithms line detection near real-time processing speed

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FPGA Implementation of Addition-based cordic-SNN With Izhikevich Neurons 35

FPGA Implementation of Addition-based CORDIC-SNN With Izhike...

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35th IEEE International System-on-Chip Conference (SOCC)

作者： Udeji, Uchechukwu Leo Margala, Martin Univ Massachusetts Lowell Elect & Comp Engn Dept Lowell MA 01854 USA Univ Louisiana Lafayette Comp & Informat Dept Lafayette LA USA

ISBN: (数字)9781665459853

ISBN: (纸本)9781665459853

When implementing a Spiking Neural Network, several neuron models can be applied, including, the integrate and fire model, the Hodgkin Huxley model, and the Izhikevich model. These models have varying properties. The integrate-and-fire model is a simplified model and does not produce many of the firing behaviors of a biological neuron to a great extent. The Hodgkin Huxley model captures several properties of a biological neuron but isn't very energy efficient due to its complexity. The Izhikevich neuron, on the other hand, is not very complex and can produce several firing behaviors seen in biological neurons. This reduced complexity of the Izhikevich neuron makes it more energy-efficient than the Hodgkin Huxley neuron, and a suitable candidate for the implementation of biologically plausible neural networks. To implement an Izhikevich neuron, two ordinary differential equations are required, one of which involves a mathematical square operation. This paper proposes an energy-efficient method of implementing a simple spiking neural network for image classification on an FPGA using the MNIST dataset. cordic (Coordinate Rotation Digital Computer) algorithm is used to implement the neuron while time-dependent backpropagation is used in training. Finally, our model is implemented on a NEXYS 4 FPGA (Field Programmable Gate Array) board to speed-up the operation of the neural network and to observe the hardware resource requirements. Results show a slight improvement in energy efficiency when a single cordic and an Izhikevich neuron implemented without cordic are compared. This resulted in a larger difference in power consumed when a larger network was implemented on an FPGA.

关键词： Spiking neural networks Izhikevich neuron model. cordic algorithm FPGA Backpropagation STDP Neuromorphic computing

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