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Digital Equalization for Cancellation of Noise-Like Interferences in Adaptive Spatial Filtering

CIRCUITS SYSTEMS AND SIGNAL PROCESSING 2017年第2期36卷 675-702页

作者： Mandal, Amritakar Mishra, Rajesh Gautam Buddha Univ Sch Informat & Commun Technol Greater Noida 201308 Uttar Pradesh India

Adaptive equalizer is an indispensable component of many radar systems for the cancellation of interference which arises due to mismatches in radar channels. This paper presents a reformulated LMS algorithm-based pipelined architecture of adaptive transversal equalizer that uses cordic as a main processing element to update angles instead of filter coefficients. In this architecture, hardware complexity has been reduced to a larger extent by utilizing pipeline method throughout the architecture. The lacuna of real-time system remains in the speed at which multiplication can be executed. We have proposed a modified version of pipelined Booth multiplier which uses partial product reduction scheme using 4-2 adder to reduce the computational time significantly. The hardware realization of the design reveals that critical path delay, area utilization and power consumption are reasonably low and therefore proposed design can be suitably be accommodated in modern-day radar system. The efficacy of the proposed interference canceller has been justified with extensive MATLAB simulations as well as hardware synthesis result for mitigation of interference in multi-channel radar systems.

关键词： Interference canceller LMS algorithm cordic algorithm Transversal equalizer Spatial filtering Radar

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A high-performance, resource-efficient, reconfigurable parallel-pipelined FFT processor for FPGA platforms

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MICROPROCESSORS AND MICROSYSTEMS 2018年第Jul.期60卷 96-106页

作者： Ngoc Hung Nguyen Khan, Sheraz Ali Kim, Cheol-Hong Kim, Jong-Myon Univ Ulsan Sch Elect Elect & Comp Engn Bldg 793 Daehak Ro Ulsan 680749 South Korea Chonnam Natl Univ Sch Elect & Comp Engn Kwangju 500757 South Korea

The fast Fourier transform (FFT) algorithm is widely used in digital signal processing systems (DSPs);hence, the development of a high-performance and resource-efficient FFT processor that conforms to the processing and precision requirements of real-time signal processing is highly desirable. We propose an FFT processor for field programmable gate array (FPGA) devices, based on the radix-2-decimation-in-frequency (R2DIF) algorithm. An appropriately modified parallel double-path delay commutator (DDC) architecture for radix-2 with continuous dual-input and dual-output streams (CoDIDOS) is proposed to increase throughput and reduce latency in FFT computation. The chip-area of the proposed design is reduced by decreasing the memory footprint of the complex twiddle factor multipliers. A multiplication scheme based on a combination of the unrolled coordinate rotation digital computer (cordic) and the canonical signed digit-based binary expression (CSDBE) is used to multiply the complex twiddle factors without requiring memory blocks for their storage. The CSDBE technique is proposed to optimize the multiplication of constants in the architecture. The proposed FFT processor is implemented as an intellectual property (IP) core and tested on a Xilinx Virtex-7 FPGA. Experimental results confirm that the proposed design improves the speed, latency, throughput, accuracy, and resource utilization of computation on FPGA devices over existing designs.

关键词： FFT Radix-2 DIF DDC architecture Parallel-Pipelined cordic algorithm CSDBE FPGA

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Bit parallel - iterative circuit for robotic application

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IEICE ELECTRONICS EXPRESS 2012年第6期9卷 443-449页

作者： Velrajkumar, Pitchandi Senthilpari, C. Ramanamurthy, G. Wong, E. K. Multimedia Univ Fac Engn & Technol Jalan Ayerkeroh Lama 75450 Melaka Malaysia

The real time anticipation of robotic task is important in finding and correcting the error in CPU of robot, which may designed using by bit parallel-iterative cordic circuit. This paper proposed pass transistor logic based multiplexer, register, full adder and basic logic gates that are implemented into bit parallel-iterative cordic basic circuits. The circuits are designed using by DSCH2 CAD tool and layout are generated by microwind 3 CAD tool. The parameter analysis done by BSIM4 analyzer. The CPL cordic circuit is compared with conventional and CMOS cordic circuits that give better performance in terms of speed, power consumption and area. The analyses are extended to Fast Fourier Transformation (FFT).

关键词： robot bit parallel-iterative cordic algorithm FFT PTL

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Simulation and experimental investigation about interferometric optical fiber acoustic sensor for sensitivity enhancement

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MEASUREMENT 2019年 137卷 556-561页

作者： Moradi, Hamed Hosseinibalam, Fahimeh Hassanzadeh, Smaeyl Univ Isfahan Dept Phys Esfahan 81746 Iran

In this paper, the results of simulation and experimental investigation of interferometric optical fiber acoustic sensing are primarily presented, and the main area of interest is studying the different algorithms for enhancement of sensor sensitivity. In fact, when light propagates through optical fiber, in a Michelson interferometer, the phase of light changes due to effect of external perturbation as acoustic wave on optical path length and this phase change is detected by demodulation algorithm. It is strived to present the Phase Generated Carrier (PGC) demodulation algorithm based on Differential-Cross-Multiplying (DCM), Arctangentfunction (ATAN) and ATAN based on Coordinate Rotation Digital Computer cordic algorithm. Simulation results reveal that PGC demodulation method based on ATAN cordic algorithm has better result (signal to noise ratio) than DCM and ATAN without using cordic algorithm. On this account, PGC demodulation algorithm based on ATAN method with cordic algorithm is applied in the experimental investigation due to simulation results and simpler digital implementation on Field Programmable Gate Array (FPGA). Moreover, acoustic frequency is detected as sidebands of harmonics of phase modulator frequencies. The sensitivity of digital circuit is 5 mu rad Hz(-0.5) and the minimum detectable phase is 50 mu rad Acoustic frequency is detected as sidebands of harmonics of phase modulator frequencies, and consequently, the system allows detecting the sinusoidal acoustic wave with different frequencies. It is also detected acoustic frequency by measurement of the reflected optical power. Moreover, in this part, it is packaged sensing arm of interferometer with polymer material (polyurethane) for investigation the effect of polymer on sensitivity enhancement of sensor. It is observed with applying of acoustic wave, the reflected optical power decreases and this reduction is more, when sensing arm is packaged with polymer. (C) 2019 Elsevier Ltd. All rights re

关键词： Optical fiber acoustic sensor Interferometry Demodulation cordic algorithm Reflected power

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Field-programmable gate array implementation of an all-digital IEEE 802.15.4-compliant transceiver

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INTERNATIONAL JOURNAL OF ELECTRONICS 2010年第12期97卷 1361-1378页

作者： Cornetta, Gianluca Touhafi, Abdellah Santos, David J. Vazquez, Jose M. Univ CEU San Pablo Dept Comp Engn & Telecommun Madrid Spain Erasmus Hogesch Dept Ind Sci & Technol Brussels Belgium Vrije Univ Brussel Dept Elect & Comp Engn Brussels Belgium

An architecture for a low-cost, low-complexity digital transceiver is presented in this article. The proposed architecture targets the IEEE 802.15.4 standard for short-range wireless personal area networks and has been implemented as a synthesisable VHDL register transfer level description. The system has been evaluated and tested using a Xilinx 90nm Virtex-4 field-programmable gate array as the target technology. Bit error rate (BER) and error vector magnitude (EVM) have been used as the figures of merit for modem performance. Simulations show that the recommended minimum BER is achieved at Eb/N0=8.7dB, whereas the EVM is 19.5%. The implemented device occupies 10% of the target FPGA and has a normalised maximum power consumption of 44mW in transmit mode and 53mW in receiver mode.

关键词： digital transceivers IEEE 802 15 4 (ZigBee) feed-forward frequency estimation Kay algorithm cordic algorithm

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Accelerating Parallel Jacobi Method for Matrix Eigenvalue Computation in DOA Estimation algorithm

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IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY 2020年第6期69卷 6275-6285页

作者： Shi, Zhiguo He, Qianwen Liu, Ying Zhejiang Univ Coll Informat Sci & Elect Engn Hangzhou 310027 Peoples R China Alibaba Zhejiang Univ Joint Inst Frontier Technol Hangzhou 310024 Peoples R China

The calculation of eigenvalues of a matrix is required by many algorithms. Specifically, it is the key technique in subspace-based direction of arrival (DOA) estimation algorithms, e.g., multiple signal classification (MUSIC). The calculation of the eigenvalues therefore directly affects the real-time implementation of DOA estimation approaches. However, the classical Jacobi methods are time-consuming. In literature, a parallel implementation has been adopted to accelerate the calculation of eigenvalues. In this paper, we propose to further decrease the execution time of this parallel method. In particular, each parallel unit of the proposed method uses one coordinate rotation digital computer (cordic) period per iteration, while more are required by the traditional counterparts, such that the eigenvalue decomposition of the MUSIC algorithm can be accelerated. In addition, the proposed method is implemented in an FPGA platform. The experimental results show that the proposed method is more computationally efficient.

关键词： Eigenvalue Jacobi method cordic algorithm FPGA parallel computation

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A Low-Power Baseband ASIC for an Energy-Collection IR-UWB Receiver

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2009年第6期44卷 1721-1733页

作者： Barras, David Meyer-Piening, Robert von Bueren, George Hirt, Walter Jaeckel, Heinz ETHZ Swiss Fed Inst Technol Elect Lab CH-8092 Zurich Switzerland Sensirion AG CH-8712 Stafa Switzerland IBM Corp Zurich Res Lab CH-8803 Ruschlikon Switzerland

This paper reports on the realization and the characterization of an application-specific integrated circuit (ASIC) intended for the processing of impulse radio ultra-wideband (IR-UWB) baseband signals. The incoming baseband signals result from the direct down-conversion of IR-UWB radio-frequency pulses, which are modulated by a binary frequency-shift keying (BFSK) scheme. The realized mixed-signal integrated circuit features an analog demodulation based on the quadri-correlation method, a non-coherent pulse detector using an integrate-and-dump operation and a bit-level synchronization digital circuit. An novel acquisition algorithm intended for low duty-cycled IR-UWB signals enabling a signal-to-noise ratio (SNR) estimate is proposed. The baseband ASIC is able to demodulate, acquire and decode BFSK IR-UWB signals. It requires 13 mW of supply power during the initial acquisition and 6.5 mW during the signal tracking phase at a pulse repetition rate (PRR) of 5 MHz. The circuit is fabricated in a 0.18-mu m CMOS technology.

关键词： Acquisition baseband processor BER cordic algorithm non-coherent demodulation quadricorrelation SNR estimate synchronization ultra-wideband (UWB)

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An Empirical Evaluation of Enhanced Performance Softmax Function in Deep Learning

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IEEE ACCESS 2023年 11卷 34912-34924页

作者： Mehra, Sumiran Raut, Gopal Purkayastha, Ribhu Das Vishvakarma, Santosh Kumar Biasizzo, Anton Indian Inst Technol Indore Dept Elect Engn Indore 453552 India Jozef Stefan Inst Ljubljana 1000 Slovenia

This article present a highly efficient and performance-enhanced Softmax Function (SF) designed for a deep neural network accelerator. The SF is an essential component of deep learning models, primarily used in the classification layer, and also in hidden layers of advanced neural networks like Transformer and Capsule networks. The primary challenge of designing an efficient hardware architecture for SF is the complex exponential and division computational sub-blocks. To address this challenge, a hardware-optimized pipelined cordic-based architecture is proposed, leveraging the mutual exclusivity of the CO-ordinate Rotational DIgital Computer (cordic) algorithm, designed for enhanced throughput, area, and power. To maintain good accuracy in deep learning models, the proposed SF design undergoes a Pareto study that evaluates the variation of accuracy concerning the number of pipeline stages. The proposed design is quantized to 16-bit precision, and inference accuracy is validated for different datasets. The SF is prototyped using Xilinx Zynq FPGA, operating at 685MHz, and ASIC implementation is performed for 45nm technology node at 5GHz of maximum operating frequency. The design achieves a validation accuracy loss of less than 2% while reducing silicon area and Energy-Delay-Product (EDP) by $12\times $ . Post-synthesis simulation results indicate that the proposed design outperforms state-of-the-art architectures, achieving $3\times $ better performance in terms of area, power, and logic delay.

关键词： Computer architecture Throughput Hardware Pipeline processing Computational modeling Iterative algorithms Propagation delay Softmax function (SF) cordic algorithm deep learning hardware optimization performance enhancement pipeline stages

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Versatile digital architecture for mobile terminal

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MICROPROCESSORS AND MICROSYSTEMS 2015年第6期39卷 405-417页

作者： Benhaoues, A. Toumi, S. Tanougast, C. Bourennane, E. Messaoudi, K. Mayache, H. Univ Badji Mokhtar LERICA Lab Annaba Algeria Univ Lorraine ASEC LCOMS Lab Metz France Univ Bourgogne LE2I Lab Dijon France

Nowadays, modern communication systems require higher data throughput to transmit increasing flow of data. Since mobile terminal needs to support multiple radio technologies, the current challenge is to design and engineering of new digital and adaptive generic architectures. In addition these versatile architectures are able to take over of many functions, which leads to avoid the use of many circuits for these different functions. In this paper, we have identified similarities between the despreader unit in Rake receiver, the FFT-SDF (Fast Fourier Transform-Single path Delay Feedback) and the cordic (Coordinate Rotation Digital Computer) algorithm to propose a generic architecture shared between these three widely used algorithms (architectural synthesis based on common operators technique). The proposed synthesizable architecture is coded using VHDL onto a Virtex-5 Field-Programmable Gate Array (FPGA) device and results are compared with FPGA implementations of similar works that share some common functionality. The implementation demonstrates that the proposed architecture can deliver a high reduction of the FPGA logic requirements with high maximum work frequency. (C) 2015 Elsevier B.V. All rights reserved.

关键词： Generic hardware architectures Rake receiver FFT-SDF cordic algorithm Common Operators technique Optimized architectural synthesis

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A multicarrier QAM modulator

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2000年第1期47卷 1-10页

作者： Vankka, J Kosunen, M Sanchis, I Halonen, KAI Aalto Univ Elect Circuit Design Lab FIN-02015 Espoo Finland

A multicarrier quadrature amplitude modulation (QAM) modulator has been developed and implemented with programmable logic devices. The multicarrier QAM modulator contains four cordic-based QAM modulators. A conventional QAM modulator needs two multipliers, one adder, and sine/cosine ROM's, The designed cordic-based QAM modulator has about the same logic complexity as the two multipliers and the adder with the same word sizes, Each QAM modulator accepts 13-bit in-phase and quadrature data streams, interpolates them by 16, and upconverts the baseband signal to a selected center frequency. The frequencies of the four carriers can be independently adjusted. The proposed multicarrier QAM modulator does not use an analog I/Q modulator, and therefore, the difficulties of adjusting the de offset, phasing, and the amplitude levels between the in-phase and quadrature-phase signal paths are avoided. The multicarrier QAM modulator is designed to fulfill the spectrum and error vector magnitude (EVM) specifications of the wideband code-division multiple-access (WCDMA) system. The simulated EVM is 1.06% root mean square (rms), well below the specified 12.5% rms for WCDMA, The measured ratio of the integrated first/second /third adjacent channel power (4.096-MHz bandwidth) to the integrated channel power (4.096-MHz bandwidth) is -68.16/-68.24/-66.17 dB versus the specified -45/-55/-55 dB.

关键词： cordic algorithm multicarrier programmable logic devices quadrature amplitude modulation wideband code-division multiple access

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