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IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 2009年第2期55卷 685-689页

作者： Wu, Zhigang Sha, Jin Wang, Zhongfeng Li, Li Gao, Minglun Nanjing Univ Dept Phys Inst VLSI Design Nanjing 210093 Peoples R China Oregon State Univ Sch EECS Corvallis OR 97331 USA

This paper presents an efficient architecture for computing the eight-point 1-D scaled DCT (Discrete Cosine Transform) with a new algorithm based on a selected Loeffler DCT scheme whose multiplications are placed in the last stage. The proposed DCT architecture does not require any scaling compensation in the computation. Furthermore, a multiplication approximation method is developed, which is, more efficient than traditional cordic (Coordinate Rotation Digital Computer) -based algorithms. Compared to the latest work [8], the proposed approach can save 14% addition operations for the same precision requirement and the path delay can be significantly reduced as well.(1)

关键词： DCT Scaled DCT cordic algorithm

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Field Programmable Gate Arrays Based Real Time Robot Arm Inverse Kinematic Calculations and Visual Servoing

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ELECTRICA 2018年第2期18卷 143-150页

作者： Celik, Baris Ak, Ayca Topuz, Vedat Marmara Univ Sch Engn Dept Elect Elect Engn Istanbul Turkey Marmara Univ Vocat Sch Tech Sci Istanbul Turkey

Reliability and precision are very important in space, medical, and industrial robot control applications. Recently, researchers have tried to increase the reliability and precision of the robot control implementations. High precision calculation of inverse kinematic color based object recognition, and parallel robot control based on field programmable gate arrays (FPGA) are combined in the proposed system. The precision of the inverse kinematic solution is improved using the coordinate rotation digital computer (cordic) algorithm based on double precision floating point number format. Red, green, and blue (RGB) color space is converted to hue saturation value (HSV) color space, which is more convenient for recognizing the object in different illuminations. Moreover, to realize a smooth operation of the robot arm, a parallel pulse width modulation (PWM) generator is designed. All applications are simulated, synthesized, and loaded in a single FPGA chip, so that the reliability requirement is met. The proposed method was tested with different objects, and the results prove that the proposed inverse kinematic calculations have high precision and the color based object recognition is quite successful in finding coordinates of the objects.

关键词： Video processing robot arm control inverse kinematic cordic algorithm field programmable gate arrays

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Advanced Phase Estimation and Design for Next-Generation Radar Systems: A Digital Approach

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TRAITEMENT DU SIGNAL 2024年第2期41卷 827-833页

作者： Sivaprasad, Ponduri Venkataraman, Anandi Murty, P. Satyanarayana RVR&JC Coll Engn ECE Dept Guntur 522019 Andhra Pradesh India Visvesvaraya Technol Univ Belagavi 590018 Karnataka India Ramaiah Inst Technol ECE Dept MSRIT Post Bangalore 560054 Karnataka India Gonna Inst Informat Technol & Sci Visakhapatnam 530053 Andhra Pradesh India

Recent advancements in radar technology necessitate the development of effective digital designs to enhance productivity and reliability, thereby accelerating radar-based applications. This study focuses on the integration of highly accurate phase degree estimation, taking into account the diverse wireless standards prevalent in space applications. Field-Programmable Gate Arrays (FPGAs) in the semiconductor industry, known for their adaptability and scalability, play a pivotal role in advancing space design modeling. This paper presents an analysis of various design challenges encountered in implementing radar systems, introducing a novel approach for milli-degree phase approximation coupled with hardware optimization. The research introduces an enhanced floating-point arithmetic model with double precision, specifically designed to address minute phase errors in time-variant analog signals. The system under investigation examines fundamental signals, including amplitude, frequency, and phase measurements, in relation to the developed sample blocks. High-performance phase approximation design methods proposed herein address issues associated with conventional phase detection and synchronization. To overcome performance trade-offs in traditional phase-detection designs due to signal frequency variations, a cordic-based iterative phase computing system is developed. Additionally, a phase correction mechanism is designed for precise milli-degree phase estimation. This comprehensive approach not only refines phase estimation techniques but also contributes significantly to the field of radar applications, particularly in the context of digital system design and signal processing.

关键词： radar system design Field-Programmable Gate Array (FPGA) milli-degree phase estimation cordic algorithm digital signal processing

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Fast implementation of direct robot kinematics with cordic systolic arrays

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INTERNATIONAL JOURNAL OF COMPUTER MATHEMATICS 1998年第3-4期67卷 239-260页

作者： Mertzios, BG Democritus Univ Thrace Dept Elect & Comp Engn Automat Control Syst Lab GR-67100 Xanthi Greece

This paper deals with fast implementation of the direct kinematics equations of robotic manipulators, using systolic arrays that incorporate one cordic rotor in their processing elements. The rotation or the translation motions of che links are implemented by using a processing element of general form. The processing elements used for the revolute joints incorporate one cordic rotor and at most an adder and one inverter. The processing elements used for the prismatic joints incorporate at most two adders and one inverter. The overall systolic architecture is derived by cascading the processing elements that correspond to the successive links and pipelining the unidirectional linear array. The use of systolic arrays with cordic processors results into fast pipelined VLSI architectures, which may be used as peripheral devices to a host digital computer and are suitable for computation of the kinematic equations, in run-time operation.

关键词： systolic arrays cordic algorithm pipelining robot kinematics

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High radix BKM algorithm

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NUMERICAL algorithmS 2004年第1-4期37卷 113-125页

作者： Didier, LS Rico, F Lab Informat Paris 6 F-75005 Paris France

In this paper, a high radix implementation of the BKM algorithm is introduced. The BKM algorithm is a shift-and-add cordic-like algorithm that performs fast computation of complex exponential and logarithm without any scalling factor. The proposed implementation reduces the number of iterations needed for the calculation. Compared to previous implementations of high radix BKM algorithm, it needs smaller lookup tables.

关键词： elementary function cordic algorithm computer arithmetic high radix

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Generation scheme of chirp scaling phase functions based on floating-point cordic processor

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JOURNAL OF ENGINEERING-JOE 2019年第21期2019卷 7436-7439页

作者： Fang, Linlin Xie, Yizhuang Li, Bingyi Chen, He Beijing Inst Technol Sch Informat & Elect Radar Res Lab Beijing 100081 Peoples R China Beijing Key Lab Embedded Real Time Informat Proc Beijing 100081 Peoples R China

This study presents a chirp scaling (CS) phase function generation scheme based on cordic algorithm, it adopts single precision floating-point cordic processor to implement a variety of non-linear operations which are involved in CS synthetic aperture radar (SAR) imaging algorithm. We extend the range of convergence of cordic algorithm and reduce the data width in rotation unit module by adopting a hardware resource reduction scheme. We also adopt a unified cordic processor to achieve square root, multiplication, and division operation, which can substitute multiple single-function processors and simplify the complicate arithmetic in CS algorithm. As a proof of concept, we verify the performance of the proposed design scheme on Xilinx XC7VX690T FPGA platform, it is also applied to 16384 x 16384 points target SAR imaging system, the FPGA resource occupancy of the CS phase function generation module demonstrates that the usage of cordic processor can effectively save the consumption of hardware resources, and the maximum operating frequency is acceptable. The accuracy of phase functions can satisfy the engineering requirements.

关键词： synthetic aperture radar floating point arithmetic field programmable gate arrays radar imaging logic design function generators chirp scaling phase functions chirp scaling phase function generation scheme cordic algorithm single precision floating-point cordic processor nonlinear operations hardware resource reduction scheme unified cordic processor division operation Xilinx XC7VX690T FPGA platform SAR imaging system CS synthetic aperture radar imaging algorithm multiplication operation square root operation

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SPECTRON: Streaming Processor Specific for Adaptronic and Biomeditronic Applications

SPECTRON: Streaming Processor Specific for Adaptronic and Bi...

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5th Biomedical Engineering International Conference (BMEiCON)

作者： Samman, Faizal Arya Surapong, Pongyupinpanich Univ Hasanuddin Makassar Fac Engn Dept Elect Engn Jl Perintis Kemerdekaan Km 10 Tamalanrea 90245 Makassar Indonesia Ramkhamhang Univ Fac Engn Dept Comp Engn Bangkok 10240 Thailand

ISBN: (纸本)9781467348904;9781467348911

This paper presents a streaming processor specifically designed for adaptronic and biomedical engineering applications. The main characteristics of the streaming processor are the flexibility to implement floating-point-based scientific computations commonly performed in the digital signal processing application. The floating-point operators are connected to dual-port memories through separated 3 operand-buses and 2 resultant-buses. Synthesized with 130-nm technology, the Spectron can be clocked at 480 MHz. The processor can perform 4 parallel streaming/pipeline floating-point operations using its FPMAC and cordic cores, resulting in a performance of about 4 x 485 = 1.94 GFlops (Giga Floating-point operation per second), which is suitable for high performance image processing in biomedical electronic engineering applications.

关键词： TermsReconfigurable Streaming Processor Adaptive Signal Processing Floating-Point Arithmetic cordic algorithm Biomedical Electronic Engineering Adaptronic

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Design and Implementation of FPGA based Linear All Digital Phase-Locked Loop

Design and Implementation of FPGA based Linear All Digital P...

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Annual IEEE India Conference (INDICON)

作者： Das, Abhishek Dash, Suraj Sahoo, A. K. Babu, B. Chitti Natl Inst Technol Dept Elect & Commun Engn Rourkela 769008 India Natl Inst Technol Dept Elect Engn Rourkela 769008 India

ISBN: (纸本)9781467322706;9781467322713

This paper presents a linear all-digital phase locked loop based on FPGA. In this ADPLL the phase detection system is realized by generating an analytic signal using a compact implementation of Hilbert transform and then simply computing the instantaneous phase using cordic algorithm in vectoring mode of operation. A 16-bit pipelined cordic algorithm is employed in order to obtain the phase information of the signal. All the components used in this phase detection system are realized as digital discrete time components. This design does not involve any class of multipliers thus reducing the complexity of the design. The loop filter of the ADPLL has been designed using PI controller which has a low pass behavior and is used to discard the higher order harmonics of the error signal. The cordic algorithm in its rotation mode of operation is used to compute sinusoidal values for the DDS. The ADPLL model has been implemented using Xilinx ISE 12.3 and ModelSim PE Student Edition 10.1a.

关键词： Phase detector Hilbert Transform cordic algorithm Phase locked loop Signal processing FPGA Implementation

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Arbitrary Waveform Generator for Radar Simulator

Arbitrary Waveform Generator for Radar Simulator

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International Conference on Computing, Power and Communication Technologies (GUCON)

作者： Gupta, Abhishek Mahajan, Anurag Aurobindo, K. Symbiosis Inst Technol Engn Elect & Telecommun Pune Maharashtra India IIT Atmospher & Microwave Syst Div SAMEER Powai India

ISBN: (纸本)9789811503399;9789811503382

The research presents design and performance verification of a high-speed programmable pulse generator based on an integrated Direct Digital Synthesizer (DDS). The generator can produce pulses with an Arbitrary Waveform Modulation of instantaneous frequency up to 11 MHz. Its primary purpose is to generate various radar waveforms with user-defined pulse widths, PRTs, modulation bandwidths (if using modulation schemes within the pulse duration), and amplitude shaping. The waveforms are required to be generated in synchronization with the radar system's timing signals. It is desirable to generate pulsed waveforms at higher Ifs;the upper limit is determined by the FPGA's master clock. The waveform generator can be used as a transmit unit as well as a radar return signal simulator. Multiple channels on the board can provide simultaneous modes.

关键词： Arbitrary Waveform Generator (AWG) Direct digital synthesis cordic algorithm Spartan-6 FPGA VHDL

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ASIC design of low-power reconfigurable FFT processor

ASIC design of low-power reconfigurable FFT processor

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7th International Conference on ASIC

作者： Liu, Guihua Feng, Quanyuan SW Jiao Tong Univ Inst Microelect Chengdu 610031 Sichuan Peoples R China

ISBN: (纸本)9781424411313

An improved ASIC design of a low-power reconfigurable FFT processor for handling high speed digital signal is proposed Radix 2-4-4-8-8 pipeline structure is chosen to achieve low complexity of hardware and high reconfigurable flexibility. The improved data access makes pipeline architecture be reconfigured as 64, 128, 256, 512, 1024 or 2048 points computation. By optimizing the pipeline of complex multiplication and power consumption, the method based on cordic algorithm are adopted to achieve a low-power FFT processor and results in a substantial savings in hardware resources and the. amount of delay elements. The ASIC design is synthesized, placed and routed using Synopsys with SMIC CMOS 0.18 mu m library. Compared to other designs, this design succeeds in arriving at the goal of high speed low power and reconfigurablility.

关键词： FFT (Fast Fourier Transform) processor ASIC pipeline cordic algorithm

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