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ReLAccS: A Multilevel Approach to Accelerator design for Reinforcement Learning on FPGA-Based systems

IEEE TRANSACTIONS ON COMPUTER-AIDED design OF INTEGRATED CIRCUITS AND systemS 2021年第9期40卷 1754-1767页

作者： Baranwal, Akhil Raj Ullah, Salim Sahoo, Siva Satyendra Kumar, Akash Tech Univ Dresden D-01062 Dresden Germany

Reinforcement learning (RL), specifically Q-learning, with human-like learning abilities to learn from experience without any a priori data, is being increasingly used in embedded systems in the field of control and navigation. However, finding the optimal policy in this approach can be highly compute-intensive, and a software-only implementation may not satisfy the application's timing constraints. To this end, we propose optimization methods at multiple levels of accelerator design for RL. Specifically, at the architecture-level, we exploit the instruction-level parallelism and the spatial parallelism in FPGAs to improve the throughput over stateof-the-art designs by up to 34%. Further, we propose lookup table-level optimizations to reduce the resource utilization and power dissipation of the accelerator. Finally, we propose algorithm-level approximation that can be used for acceleration of Q-learning problems with more states and for reducing the peak power dissipation. We report up to 10x reduction in power dissipation with marginal degradation in quality of results.

关键词： cross-layer system design embedded systems field-programmable gate array (FPGA) high-level synthesis reinforcement learning (RL)

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CLEO-CoDe: Exploiting Constrained Decoding for cross-layer Energy Optimization in Heterogeneous Embedded systems 29

<i>CLEO-CoDe</i>: Exploiting Constrained Decoding for Cross-...

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29th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)

作者： Sahoo, Siva Satyendra Kumar, Akash Tech Univ Dresden Ctr Adv Elect Dresden CfAED Chair Processor Design Dresden Germany

ISBN: (纸本)9781665426145

system-level design for low-power and energy efficiency in embedded systems using Heterogeneous Multi-Processor system-on-Chip (HMPSoC) is a challenging task due to the large design space. The related design Space Exploration (DSE) suffers from scaling due to various degrees of freedom across multiple layers of the compute stack. Traditional multi-objective meta-heuristic approaches work well for unconstrained system-level design, but do not scale well with the additional system and user constraints. Using a SATisfiablity problem (SAT) solver as a decoder for the meta-heuristics has been explored in related research as a better solution for a discrete constrained multi-objective optimization problem. This approach restricts the problem to the feasible space, hence improving the quality of the results. In this paper, we explore the ways in which constrained decoding such as the SAT decoding approach can be leveraged for cross-layer design space exploration. Low-power methodologies such as Dynamic Voltage and Frequncy Scaling (DVFS) and application-specific implementations are integrated, thus scaling the design space. Additionally, we demonstrate how user constraints on the system synthesis problem can be learned by our proposed approach to prune the meta-heuristic design space and improve the quality of the solutions. As the constraints on the problem increase and the design space scales, the constrained decoding approach outperforms a typical meta-heuristic approach.

关键词： cross-layer system design Energy-efficient design system-level design Embedded systems

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Using Monte Carlo Tree Search for EDA - A Case-study with designing cross-layer Reliability for Heterogeneous Embedded systems 29

Using <i>Monte Carlo Tree Search</i> for EDA - A Case-study ...

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29th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)

作者： Sahoo, Siva Satyendra Kumar, Akash Tech Univ Dresden Ctr Adv Elect Dresden CfAED Chair Processor Design Dresden Germany

ISBN: (纸本)9781665426145

Continued transistor scaling and increasing power density have led to considerable increase in fault-rates in silicon nanotechnology-based real-time systems. cross-layer fault tolerance techniques present a more cost-efficient methodology for adapting to such increased fault rates by distributing fault-tolerance to different layers. To this end, we propose a methodology for integrating the design space exploration (DSE) for task-mapping on heterogeneous hardware-platforms with designing cross-layer reliability. Specifically, we model the DSE for task-mapping with cross-layer reliability as a tree search problem and use Monte Carlo Tree Search for task-mapping and scheduling applications with specific reliability requirements. The proposed methodology results in considerable improvements over a standalone approach to task-mapping and implementing cross-layer reliability.

关键词： cross-layer system design Reliability Randomized Algorithms design Space Exploration system-level design Embedded systems

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CLAppED: A design Framework for Implementing cross-layer Approximation in FPGA-based Embedded systems 58

CLAppED: A Design Framework for Implementing Cross-Layer App...

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58th ACM/IEEE design Automation Conference (DAC)

作者： Ullah, Salim Sahoo, Siva Satyendra Kumar, Akash Tech Univ Dresden Ctr Adv Elect Dresden CfAED Dresden Germany

ISBN: (纸本)9781665432740

With the rising variation and complexity of embedded workloads, FPGA-based systems are being increasingly used for many applications. The reconfigurability and high parallelism offered by FPGAs are used to enhance the overall performance of these applications. However, the resource constraints of embedded platforms can limit the performance in multiple ways. In recent years, Approximate Computing has emerged as a viable tool for improving the performance by utilizing reduced precision data structures and resource-optimized high-performance arithmetic operators. However, most of the related state-of-the-art research has mainly focused on utilizing approximate computing principles individually on different layers of the computing stack. Nonetheless, approximations across different layers of computing stack can substantially enhance the system's performance. To this end, we present a framework to enable the intelligent exploration and highly accurate identification of the feasible design points in the large design space enabled by cross-layer approximations. Our framework proposes a novel polynomial regression-based method to model approximate arithmetic operators. The proposed method enables machine learning models to better correlate approximate operators with their impact on an application's output quality. We use a 2D convolution operator as a test case and present the results for FPGA-based approximate hardware accelerators.

关键词： Approximate Computing Embedded systems cross-layer system design FPGA High-level Synthesis

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