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37th IEEE VLSI Test Symposium (VTS)

作者： Zhang, Jianwei Gupta, Sandeep K. Halfond, William G. J. Univ Southern Calif Los Angeles CA 90007 USA

ISBN: (纸本)9781728111704

Test generation for digital hardware is highly automated, scalable (in practice), and provides high test quality. In contrast, current software automatic test data generation approaches suffer from low test quality or high complexity. While mutation-oriented constraint-based test data generation for software was proposed to generate high quality test data for real program bugs, all existing approaches require symbolic analysis for the whole program, and hence are not scalable even for unit testing, i.e., testing the lowest-level software modules. We propose a new method inspired by hardware d-algorithm and divide and conquer for software test data generation. To reduce runtime complexity and improve scalability, we combine global structural analysis and a sequence of small reusable symbolic analyses of parts of the program, instead of symbolically executing each mutated version of the entire program. We also propose a multi-pass test generation system to further reduce runtime complexity and compact test data. We compare our tools with one of the best software test generation tools (EvoSuite[20], which won the SBST 2017 tool competition) and demonstrate that our approach generates higher quality unit tests in a scalable manner and provides a compact set of tests.

关键词： test data generation for software d-algorithm ATPG mutation testing software testing

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A Comprehensive Test Pattern Generation Approach Exploiting the SAT Attack for Logic Locking

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IEEE TRANSACTIONS ON COMPUTERS 2023年第8期72卷 2293-2305页

作者： Zhong, Yadi Guin, Ujjwal Auburn Univ Dept Elect & Comp Engn Auburn AL 36849 USA

The need for reducing manufacturing defect escape in today's safety-critical applications requires increased fault coverage. However, generating a test set using commercial automatic test pattern generation (ATPG) tools that lead to zero-defect escape is still an open problem. It is challenging to detect all stuck-at faults to reach 100% fault coverage. In parallel, the hardware security community has been actively involved in developing solutions for logic locking to prevent IP piracy. In logic locking, locks are inserted in different locations of the netlist to modify the original functionality. Unless the correct key is programmed into the IC, the circuit functions incorrectly. Unfortunately, the Boolean satisfiability (SAT) based attack, introduced in (Subramanyan et al. 2015), can determine the secret key efficiently, and break different logic locking schemes. In this article, we propose a novel test pattern generation approach using the powerful SAT attack on logic locking. A stuck-at fault is modeled as a locked gate with a secret key, where it can effectively deduce the satisfiable assignment with reduced backtracks under key initialization of the SAT attack. The input pattern that determines the key is a test for the stuck-at fault. We propose two different approaches for test pattern generation. First, a single stuck-at fault is targeted, and a corresponding locked circuit with one key bit is created. This approach generates one test pattern per fault. Second, we consider a group of faults and convert the circuit to its locked version with multiple key bits. The inputs obtained from the SAT attack tool are the test set for detecting this group of faults. Our approach can find test patterns for all hard-to-detect faults that were previously undetected in commercial ATPG tools. The proposed test pattern generation approach can efficiently detect redundant faults as well. We demonstrate the effectiveness of the approach on ITC'99 benchmarks. The results show

关键词： ATPG d-algorithm Boolean satisfiability logic locking fault coverage

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Performance analysis of a 2-d EEG compression algorithm using an automatic seizure detection system

Performance analysis of a 2-D EEG compression algorithm usin...

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Asilomar Conference on Signals, Systems & Computers

作者： Hoda daou Fabrice Labeau Department of Electrical and Computer Engineering McGill University Montreal QUE Canada

ISBN: (纸本)9781467350501

A recently developed compression algorithm that uses dWT, SPIHT and smoothness transforms to compress EEG channels in 2-d proved to give very low distortion values for high compression ratios. Although Rd performance is a commonly used metric in signal compression, in medical signals, it is important to preserve important diagnostic information. In order to move towards such a diagnostics-oriented performance assessment, we propose in this paper a framework to evaluate the performance of EEG compression mechanisms in terms of post-compression seizure detection capability. In particular, we show that the above-mentioned 2-d algorithm can maintain diagnostic features down to bitrates of 2 bits per sample.

关键词： EEG dWT SPIHT Electroencephalography Compression algorithms compression ratio d-algorithm signal compression diagnostic message Seizures detection systems Bit rate

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POINT-LINE INTERSECTION IN PARALLEL AXES

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JOURNAL OF IMAGING SCIENCE ANd TECHNOLOGY 1995年第2期39卷 162-166页

作者： MELVILLE, Jd BURTON, RP Department of Computer Science Brigham Young University Provo Utah

Euclidean geometry is applied to the parallel axes graph after it is plotted in a plane to develop an algorithm that determines if a point intersects a line segment in the parallel axes graph. The parametric equation of a line is used to develop tests for the different cases of two-dimensional (2-d) points and lines that occur in parallel axes. The n-d algorithm is implemented by iteration of the 2-d algorithm.

关键词： layshaft d-algorithm Line sections algorithms iterative methods

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MULTIRATE 3-d SUBBANd COdING OF VIdEO

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IEEE TRANSACTIONS ON IMAGE PROCESSING 1994年第5期3卷 572-588页

作者： TAUBMAN, d ZAKHOR, A University of California Berkeley CA USA

We propose a full color video compression strategy, based on 3-d subband coding with camera pan compensation, to generate a single embedded bit stream supporting multiple decoder display formats and a wide, finely gradated range of bit rates. An experimental implementation of our algorithm produces a single bit stream, from which suitable subsets are extracted to be compatible with many decoder frame sizes and frame rates and to satisfy transmission bandwidth constraints ranging from several tens of kilobits per second to several megabits per second. Reconstructed video quality from any of these bit stream subsets is often found to exceed that obtained from an MPEG-1 implementation, operated with equivalent bit rate constraints, in both perceptual quality and mean squared error. In addition, when restricted to 2-d, the algorithm produces some of the best results available in still image compression.

关键词： subband coding Image compression d-algorithm decoders megabits per second data compression megabit Videotapes bit stream

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SCATTER CORRECTION IN 3-d PET

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IEEE TRANSACTIONS ON MEdICAL IMAGING 1994年第4期13卷 649-657页

作者： LERCHER, MJ WIENHARd, K MAX PLANCK INST NEUROL RES D-50931 COLOGNEGERMANY

Modern multiring positron emission tomographs allow the acquisition of 3-d data sets to increase their sensitivity. A substantial part of this data is due to scattered radiation. We describe the experimental dependence of point source scatter distributions on energy window setting, source location, and scatter volume in geometries relevant for brain studies. The point source scatter distribution was parametrized accurately by a broad, 2-d Gaussian, which included a shift parameter to account for asymmetry of the scatter medium relative to the source. This parametrization was used to formulate two fast scatter correction algorithms suitable for brain scans. In both algorithms, a 2-d subset of the measured projections was transformed into a scatter projection, An image of the 3-d scatter distribution was reconstructed using 2-d algorithms. It was then subtracted from the total (true + scattered) 3-d image. Both algorithms were implemented in different combinations with the additional attenuation correction and were tested on point source and phantom measurements. It was shown that, for the situation typical for brain scans, reconstructed scatter fractions could be reduced to 5% or less.

关键词： Point sources Cerebrum Position measurement d-algorithm Three-dimensional Images algorithms Positron emission Brain Imaging

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Extended selection of switching target faults in CONT algorithm for test generation

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Journal of Electronic Testing: Theory and Applications (JETTA) 1990年第3期1卷 183-183页

作者： Takamatsu, Y. Kinoshita, K. Department of Computer Science Faculty of Engineering Ehime University Matsuyama Japan Department of Applied Physics Faculty of Engineering Osaka University Suita Japan

We describe an extended selection of switching target faults in the CONT algorithm. The main difficulty in test generation is the conflict that arises in the process of determining the signal values due to reconvergent fanouts. Conventional approaches for test generation change a signal value, which causes conflicts to another possible choice for backtracking. In the CONT algorithm, a strategy of switching target fault was proposed as a new backtracking mechanism. In this method, the target fault is switched to a new target fault instead of making an alternative assignment on the primary input value when a conflict occurs. A disadvantage of the CONT algorithm is that unjustified lines exist in the process of test generation. These unjustified lines make the procedure of switching targets complicated and restrict the possible choice in selecting the new target fault. In the new version of CONT, called CONT-2, we have removed the unjustified lines in the process of test generation and have extended to two target-fault types for switching targets. Implementing CONT-2 by a Fortran program, ISCAS85 benchmark circuits are examined. Experiments on a combined system with fault simulation followed by CONT-2 are also presented.

关键词： d-algorithm fault simulation fault target switching

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MOS TEST PATTERN GENERATION USING PATH ALGEBRAS

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IEEE TRANSACTIONS ON COMPUTERS 1987年第9期36卷 1123-1128页

作者： dAMPER, RI BURGESS, N Department of Electronics and Computer Science University of Southampton Southampton S0 5NH United Kingdom.

There is extensive evidence that the classical, stuck-at fault model, operating at the gate level, is inadequate for testing MOS VLSI circuits. By contrast, a ``nonclassical,"" switch-level modelÂ¿directly representing open and short circuits in the interconnect and transistors stuck-open or stuck-onÂ¿allows important effects such as MOSFET bidirectionality and tristate behavior to be taken into account. This paper describes a new switch-level method for generating the singular cover of an MOS primitive gate using path algebras. The method yields tests to cover all specified interconnect open and short circuits, and all irredundant transistor stuck-open and stuck-on faults, should such tests exist. It relies on specification of an appropriate algebra by redefinition of the operators used in computing powers of a matrix. Two such algebras are requiredÂ¿one to generate tests for open circuit faults and the other for short circuit faults. Test generation for networks of primitive gates is achieved in two stages: after deriving singular covers for the primitives, a variant of the d-algorithm with modified ``d-drive"" is used. The approach is unified and powerful, having the potential to detect parasitic latch behavior and to generate tests for any of the current MOS VLSI technologies. In common with most present automatic test generation methods, it is restricted to combinational logic. Practical limits on the size of circuit which can be dealt with appear comparable to those set by use of the classical d-algorithm.

关键词： d-algorithm MOS circuits fault models graph theory path algebras test pattern generation

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MOdELING ANd TEST-GENERATION algorithmS FOR MOS CIRCUITS

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IEEE TRANSACTIONS ON COMPUTERS 1985年第5期34卷 426-433页

作者： JAIN, SK AGRAWAL, Vd AT& T Bell Laboratories

An application of the d-algorithm in generating tests for MOS circuit faults is described. The MOS circuits considered are combinational and acyclic but may contain transmission gates and buses. Tests are generated for both the stuck type faults and the transistor faults (open and short). A logic model is derived for the MOS circuits. In addition to the conventional logic gates, a new type of modeling block is used to represent the "memory" state caused by the "open" transistors. Every fault, whether a stuck type fault or a transistor fault, is represented in the model as a stuck fault at a certain gate input. For generating tests, however, the d-algorithm needs modification. The singular cover and the d-cubes for the new gate include some memory states. To handle the memory state, an initialization procedure has been added to the consistency part of the d-algorithm. The procedure of modeling and test generation is finally extended to transmission gates and buses.

关键词： d-algorithm MOS circuits integrated circuit testing test generation transistor faults

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TESTING STRATEGY ANd TECHNIQUE FOR MACRO-BASEd CIRCUITS

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IEEE TRANSACTIONS ON COMPUTERS 1985年第1期34卷 85-90页

作者： SOMENZI, F GAI, S MEZZALAMA, M PRINETTO, P CTR ELABORAZ NUMERALE SEGNALI I-10129 TORINO ITALY POLITECN TORINO DIPARTIMENTO AUTOMAT & INFORMAT I-10129 TURIN ITALY

The increasing complexity of VLSI systems demands structured approaches to reduce both design time and test generation effort. PLA"s and scan paths have both been widely reported to be efficient in this sense. This correspondence presents an easily testable structure and its related testing strategies. The circuits are assumed to be based on the interconnection of combinatorial macros, mostly implemented by PLA"s; tests are generated locally, considering the involved macro as an isolated item, and then are expressed in terms of primary inputs and outputs using a topological approach as general strategy and algebraic techniques for the propagation of signals through macros. Propagation is dealt with by new algorithms. Since the problem of test generation is NP-hard, a set of heuristics is introduced to keep the amount of computation reasonable; several implementation ❉s are finally investigated.

关键词： Automated test pattern generation (ATPG) Boolean differences d-algorithm LSSd controlability design for testability observability programmable logic array (PLA) structured design

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