Nonlinear recursion is one of the most challenging classes of logic programs for efficient evaluation in logic programming systems. We identify one popular class of nonlinear recursion, regular nonlinear recursion, an...
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Nonlinear recursion is one of the most challenging classes of logic programs for efficient evaluation in logic programming systems. We identify one popular class of nonlinear recursion, regular nonlinear recursion, and investigate its efficient implementation by a deductive database approach. The approach performs a detailed query binding analysis based on query information, constraint information and the structure of a recursion, selects an appropriate predicate evaluation order and generates an efficient query evaluation plan. Interesting query evaluation techniques, such as chain-following, chain-split, and constraint pushing, are developed for the efficient evaluation of different kinds of queries. Furthermore, the technique can be extended to the evaluation of regular nonlinear recursions in HiLog and F-logic programs. The study not only presents a method for the evaluation of regular nonlinear recursions in a declarative way but also demonstrates the power of the deductive database approach in the analysis and evaluation of sophisticated logic programs.
The conventional approach for the implementation of the knowledge base of a planning agent, on an intelligent embedded system, is solely of software nature. It requires the existence of a compiler that transforms the ...
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The conventional approach for the implementation of the knowledge base of a planning agent, on an intelligent embedded system, is solely of software nature. It requires the existence of a compiler that transforms the initial declarative logic program, specifying the knowledge base, to its equivalent procedural one, to be programmed to the embedded systems microprocessor. This practice increases the complexity of the final implementation (the declarative to sequential transformation adds a great amount of software code for simulating the declarative execution) and reduces the overall systems performance (logic derivations require the use of a stack and a great number of jump instructions for their evaluation). The design of specialized hardware implementations, which are only capable of supporting logic programs, in an effort to resolve the aforementioned problems, introduces limitations in their use in applications where logic programs need to be intertwined with traditional procedural ones in a desired application. In this paper, we exploit HW/SW codesign methods to present a microprocessor, capable of supporting hybrid applications using both programming approaches. We take advantage of the close relationship between attribute grammar (AG) evaluation and knowledge engineering methods to present a programmable hardware parser that performs logic derivations and combine it with an extension of a conventional RISC microprocessor that performs the unification process to report the success or failure of logic derivations. The extended RISC microprocessor is still capable of executing conventional procedural programs, thus hybrid applications can be implemented. The presented implementation increases the performance of logic derivations for the control inference process (experimental analysis yields an approximate 1000% - 10 times increase in performance) and reduces the complexity of the final implemented code through the introduction of an extended C language called C
The N-ARCH project developed at the university of LILLE aims to design a parallel reduction machine well suited to the execution of declarative programs. One of the aspect of the project is the emulation of a parallel...
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The N-ARCH project developed at the university of LILLE aims to design a parallel reduction machine well suited to the execution of declarative programs. One of the aspect of the project is the emulation of a parallel symbolic processor based on the use of a network of Transputers. An N-ARCH kernel has been writen and runs on each node of the network. This kernel emulates the main characteristics of the N-ARCH architecture. This paper is devoted to simulation results and is composed of three parts. The first part describes the model of the N-ARCH architecture and shows the N-ARCH kernel is well suited to this model. A second part presents the structure of the simulated programs and the different parameters which have been used for them.
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