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A comparison of three sets of dsp algorithms for monitoring the production of ethanol in a fed-batch baker's yeast fermenter

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MEASUREMENT 2008年第9期41卷 970-985页

作者： Mangesh, M. Gundale Jana, Amiya K. Indian Inst Technol Dept Chem Engn Kharagpur 721302 W Bengal India Birla Inst Technol & Sci Dept Chem Engn Pilani 333031 Rajasthan India

This paper aims at presenting the design approach of three sets of dsp algorithms for a fed-batch biochemical reactor. The proposed algorithms are based on the estimation/observation methods enhanced with artificial neural networks. Here, three popular estimation schemes, namely extended Luenberger observer, extended Kalman filter and adaptive state estimator, have been designed to estimate the specific growth rate, substrate consumption rate and product formation rate on the basis of measured process state variables. The neural network model infers the biomass concentration. It is supposed that the substrate and product concentrations along with the broth volume are measured quantities. The comparative performance of the proposed dsp schemes has been inspected through simulation results dealing with a fed-batch baker's yeast fermenter. (C) 2008 Elsevier Ltd. All rights reserved.

关键词： Nonlinear state estimators Artificial neural network model dsp algorithms Fed-batch bioreactor

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High-speed and low-power reconfigurable architectures of 2-digit two-dimensional logarithmic number system-based recursive multipliers

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IET CIRCUITS DEVICES & SYSTEMS 2010年第5期4卷 374-381页

作者： Azarmehr, M. Ahmadi, M. Jullien, G. A. Muscedere, R. Univ Windsor Dept Elect & Comp Engn Windsor ON N9B 3P4 Canada

In new dsp applications, reconfigurable architectures have emerged to provide a flexible, high-performance, high-speed and low-power implementation platform for wireless embedded devices. Since some dsp algorithms rely heavily on multiplication, there are still demands for more efficient multiplication structures. In this study, two reconfigurable recursive multipliers are presented. The authors' architectures combine some of the flexibility of software with the high performance of hardware through implementing different levels of recursive multiplication schemes on a two-dimensional logarithmic number system (2DLNS) processing structure. The data are split into a number of smaller sections, where each section is converted to a 2-digit 2DLNS (2 bases) representation. The dynamic range reduction and logarithmic characteristics of computing with two orthogonal base exponents in this number system allows multiplication to be implemented with simple parallel small adders. The authors' architectures are able to perform single and double precision multiplications, as well as fault tolerant and dual throughput single precision operations. The implementations demonstrate the efficiency of 2DLNS in multiplication intensive

关键词： low-power reconfigurable architectures double precision multiplications adders dsp algorithms single precision multiplications dual throughput single precision operations dsp applications parallel small adders reconfigurable architectures recursive multiplication schemes wireless embedded devices dynamic power consumption fault tolerant embedded systems 2-digit 2D logarithmic number system reconfigurable recursive multipliers multiplication structures logarithmic characteristics orthogonal base exponents digital signal processing chips multiplying circuits dynamic range reduction 2DLNS processing structure fault tolerance

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Ultra low phase noise dsp oscillator

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IEEE SIGNAL PROCESSING MAGAZINE 2007年第4期24卷 121-124页

作者： Harris, Fred San Diego State Univ San Diego CA 92182 USA

This article describes a novel complex oscillator, which is based on an interesting variation of the traditional CORDIC DDS and produces sine and cosine output samples of any specified angle. Our oscillator provides drastically improved phase noise performance (relative to a traditional CORDIC DDS) without the need for additional CORDIC iteration processing. In addition, our oscillator supports real-time output sample-by-sample digital frequency control. In describing our enhanced complex oscillator, we first present the arithmetic processing needed to generate sine and cosine samples. Next we show how that processing is implemented using the CORDIC algorithm. Then we detail the trick used to reduce oscillator phase noise errors. Finally we show how to guarantee a stable oscillator output amplitude and present an example of our oscillator\'s ultra low phase noise performance.

关键词： digital arithmetic direct digital synthesis oscillators signal processing CORDIC iterations dsp algorithms arithmetic- processing cosine output samples direct digital synthesizer oscillator phase noise error reduction real time output sample-by-sample di Digital arithmetic digital synthesizers signal processing direct digital synthesis Oscillators Low phase noise

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Recursive anisotropic 2-D Gaussian filtering based on a triple-axis decomposition

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IEEE TRANSACTIONS ON IMAGE PROCESSING 2007年第7期16卷 1925-1930页

作者： Lam, Stanley Yin Man Shi, Bertram E. Hong Kong Univ Sci & Technol Dept Elect & Comp Engn Kowloon Hong Kong Peoples R China

We describe a recursive algorithm for anisotropic 2-D Gaussian filtering, based on separating the filter into the cascade of three, rather two, 1-D filters. The filters operate along axes obtained by integer horizontal and/or vertical pixel shifts. This eliminates interpolation, which removes spatial inhomogeneity in the filter, and produces more elliptically shaped kernels. It also results in a more regular filter structure, which facilitates implementation in dsp chips. Finally, it improves matching between filters with the same eccentricity and width, but different orientations. Our analysis and experiments indicate that the computational complexity is similar to an algorithm that operates along two axes (< 11 ms for a 512 X 512 image using a 3.2-GHz Pentium 4 PC). On the other hand, given a limited set of basis filter axes, there is an orientation dependent lower bound on the achievable aspect ratios.

关键词： directional filter dsp algorithms Gaussian filter recursive filtering

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Design and implementation of a reconfigurable architecture for dsp 5

Design and implementation of a reconfigurable architecture f...

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5th International Conference on ASIC

作者： Yang, Y Mao, ZG Lai, FC Zhao, B Xia, YF Harbin Inst Technol Ctr Microelect Harbin 150001 HeiLongJiang Peoples R China

ISBN: (纸本)078037889X

To accelerate the execution of most dsp(Digital Signal Processing) algorithms such as FFT, FIR, Vector operations, while keeping the flexibility of the chip, a reconfigurable architecture (named ReDAr) for dsp is proposed and implemented, and finally will be applied to the Radar system of Automatic Navigation Equipment. By analyzing these algorithms, the structure of Reconfigurable Processing Element (RPE), the Crossbar interconnect network, the Memory organization. the host controlling strategy, and the data sequencing scheme of the architecture are conceived. and parts of them, including the RPE, Crossbar. data sequencer, are reconfigurable. After configuration. it can be interconnected into a parallel and pipelined framework. closely matching the algorithms and like a dedicated hardware. By simulation. the performances of these algorithms mapped onto this architecture are comparative to algorithm-specific chips in market, and satisfy the requirement of the targeted application.

关键词： radar signal processing radionavigation reconfigurable architectures parallel processing pipeline processing fast Fourier transforms FIR filters ReDAr reconfigurable architecture dsp algorithms digital signal processing algorithms FFT fast Fourier transform FIR finite impulse response vector operations radar system automatic navigation equipment RPE reconfigurable processing element crossbar interconnect network memory organization data sequencing pipelined framework parallel framework

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IP protection of dsp algorithms for system on chip implementation

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IEEE TRANSACTIONS ON SIGNAL PROCESSING 2000年第3期48卷 854-861页

作者： Chapman, R Durrani, TS Univ Strathclyde Dept Elect & Elect Engn Glasgow G1 1XW Lanark Scotland

Silicon technology has now advanced to the point that there is a serious mismatch in the time taken to design advanced silicon-based systems and the time to market for any new product or product derivative. To obviate this delay, a new paradigm is emerging based on intellectual property (IP) exchange, where designers and differing companies share subsystems (virtual cores) between themselves to reduce design time to acceptable levels. To this end, over 150 companies including all the major players formed the Virtual Socket Interface Alliance in March 1997, The protection of IP has become a serious issue as intercompany subsystem design exchange becomes more commonplace, This paper presents new techniques to protect the IP of virtual cores that implement digital signal processing (dsp) algorithms, The approach involves embedding codewords into the design of fundamental signal processing algorithms such as digital filters and the DFT in such a way that proof of authorship can be retained, and, if required, easily identified. The techniques discussed can be adapted to protect other fundamental dsp algorithms such as convolution and correlation. The protection of IP via watermarking techniques is increasingly being applied at all levels of design. It is particularly advantageous if such techniques are applied at the highest abstraction levels in the design flow and if such techniques are applied at basic algorithm level, they become very difficult to detect at lower levels of system design.

关键词： dsp algorithms intellectual property system on chip VLSI design watermarking

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Address Satisfaction for Storage Files with Fifos or Stacks during Scheduling of dsp algorithms 00

Address Satisfaction for Storage Files with Fifos or Stacks ...

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Proceedings of the 13th symposium on Integrated circuits and systems design

作者： C. A. Alba Pinto K. van Eijk B. Mesman J. Jess

ISBN: (纸本)9780769508436

Tight data- and timing constraints are imposed by dsp applications. Also, the target processor architecture or the synthesized circuit template conform resource constraints. Additionally, instead of registers address-limited storage files with fifos or stacks are used. Continuing previous work on register file capacity satisfaction, this paper presents a method that during scheduling handles address constraints of storage files with fifos or stacks together with timing and resource constraints.

关键词： fifos target processor architecture digital signal processing chips synthesized circuit template processor scheduling bottleneck identification file organisation resource allocation address constraints dsp algorithms register file capacity storage allocation resource constraints stacks computer architecture storage management timing constraints storage files scheduling

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From C to netlists: hardware engineering for software engineers?

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ELECTRONICS & COMMUNICATION ENGINEERING JOURNAL 2002年第4期14卷 165-173页

作者： Alston, I Madahar, B BAE Syst Ctr Adv Technol Dept Syst Chelmsford CM2 8HN Essex England

The software programmable multiprocessor architecture has been employed extensively over the past two decades for embedded signal-processing applications. However, the increased complexity of such systems has, in many cases, required the use of hardware acceleration to meet the growing time-critical apsects of the design. Today's field-programmable gate arrays (FPGAs) offer an alternative or additional acceleration platform, especially to an application-specific integrated circuit (ASIC). However, the traditional low-level development methods, such as schematic capture or hardware description languages (HDLs), employed to implement these hardware accelerated parts of the design result in a design lifecycle mismatch between the rapid development techniques available for the software programmable parts. This paper presents high-level design languages that enable users to generate netlists for FPGAs directly from high-level C-like languages, thereby offering an equivalent programming solution to that available with microprocessors. It details how one of these languages can be integrated into a high-level design flow for the rapid development of heterogeneous embedded signal-processing systems and presents results from a benchmark.

关键词： hardware engineering FPGA Digital signal processing chips Microprocessors and microcomputers Software engineering techniques digital signal processing chips application specific integrated circuits software engineers high-level C-like languages embedded systems high-level design field-programmable gate arrays low-level development methods hardware acceleration field programmable gate arrays Logic circuits Logic and switching circuits Computer-aided circuit analysis and design high-level design languages Computer-aided logic design ASIC heterogeneous embedded signal-processing systems hardware description languages dsp algorithms High level languages digital signal-processing algorithms design lifecycle Electronic engineering computing application-specific integrated circuit netlists software programmable multiprocessor architecture logic CAD C language embedded signal-processing

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MULTIPROCESSOR IMPLEMENTATION OF REAL-TIME dsp algorithms

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1995年第3期3卷 393-403页

作者： WANG, DJ HU, YH IEEE Department of Electrical and Computer Engineering University of Wisconsin

In this paper, we consider multiprocessor implementation of real-time recursive digital signal processing algorithms. The objective is to devise a periodic schedule, and a fully static task assignment scheme to meet the desired throughput rate while minimizing the number of processors. Toward this goal, we propose a notion called cutoff time, We prove that the minimum-processor schedule can be found within a finite time interval bounded by the cutoff time. As such the complexity of the scheduling algorithm and the allocation algorithm can be significantly reduced. Next, taking advantage of the cutoff time, we derive efficient heuristic algorithms which promise better performance and less computation complexity compared to other existing algorithms. Extensive benchmark examples are tested,which yield most encouraging results.

关键词： .Processors Implementation of Real-Time dsp algorithms

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ARCHITECTURE-DRIVEN SYNTHESIS TECHNIQUES FOR VLSI IMPLEMENTATION OF dsp algorithms

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PROCEEDINGS OF THE IEEE 1990年第2期78卷 319-335页

作者： DEMAN, H CATTHOOR, F GOOSSENS, G VANHOOF, J VANMEERBERGEN, J NOTE, S HUISKEN, J PHILIPS RES LABS 5600 JA EINDHOVENNETHERLANDS INTERUNIV MICROELECTR CTR LAB B-3030 LOUVAINBELGIUM KATHOLIEKE UNIV LEUVEN INST ELEKTROTECHLOUVAINBELGIUM

The state of the art of compiling digital signal processing (dsp) algorithms into silicon is discussed. It is indicated how digital signal processing differs from numerical data processing, including the consequences for the synthesis tools. On the basis of a broad range of dsp applications, four classes of architectures are then distinguished to serve as templates for four different synthesis systems. Although each of these four silicon compilers is tuned to a specific class of applications in order to generate area-efficient chips, they all accept as input the same behavioral dsp specification. The four selected architectural styles are best characterized by hard-wired bit-serial data-paths, microcoded multiprocessors, cooperating bit-parallel data-paths, and regular arrays. The characteristics of the first three architectures are treated in more detail in a discussion of three different Cathedral synthesis environments for their respective design. A fourth Cathedral environment, aiming at the synthesis of regular arrays, is still in an early stage of development and is not discussed. The claims for the compilers are substantiated by typical designs

关键词： Cathedral synthesis environments dsp algorithms dsp chips layout VLSI VLSI implementation architectural styles architecture-driven synthesis techniques area-efficient chips behavioral dsp specification circuit layout CAD classes of architectures cooperating bit-parallel data-paths digital signal processing digital signal processing chips hard-wired bit-serial data-paths microcoded multiprocessors regular arrays silicon compilers silicon compiling synthesis tools

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