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A comparison of three sets of dsp algorithms for monitoring the production of ethanol in a fed-batch baker's yeast fermenter

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MEASUREMENT 2008年第9期41卷 970-985页

作者： Mangesh, M. Gundale Jana, Amiya K. Indian Inst Technol Dept Chem Engn Kharagpur 721302 W Bengal India Birla Inst Technol & Sci Dept Chem Engn Pilani 333031 Rajasthan India

This paper aims at presenting the design approach of three sets of dsp algorithms for a fed-batch biochemical reactor. The proposed algorithms are based on the estimation/observation methods enhanced with artificial neural networks. Here, three popular estimation schemes, namely extended Luenberger observer, extended Kalman filter and adaptive state estimator, have been designed to estimate the specific growth rate, substrate consumption rate and product formation rate on the basis of measured process state variables. The neural network model infers the biomass concentration. It is supposed that the substrate and product concentrations along with the broth volume are measured quantities. The comparative performance of the proposed dsp schemes has been inspected through simulation results dealing with a fed-batch baker's yeast fermenter. (C) 2008 Elsevier Ltd. All rights reserved.

关键词： Nonlinear state estimators Artificial neural network model dsp algorithms Fed-batch bioreactor

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IP protection of dsp algorithms for system on chip implementation

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IEEE TRANSACTIONS ON SIGNAL PROCESSING 2000年第3期48卷 854-861页

作者： Chapman, R Durrani, TS Univ Strathclyde Dept Elect & Elect Engn Glasgow G1 1XW Lanark Scotland

Silicon technology has now advanced to the point that there is a serious mismatch in the time taken to design advanced silicon-based systems and the time to market for any new product or product derivative. To obviate this delay, a new paradigm is emerging based on intellectual property (IP) exchange, where designers and differing companies share subsystems (virtual cores) between themselves to reduce design time to acceptable levels. To this end, over 150 companies including all the major players formed the Virtual Socket Interface Alliance in March 1997, The protection of IP has become a serious issue as intercompany subsystem design exchange becomes more commonplace, This paper presents new techniques to protect the IP of virtual cores that implement digital signal processing (dsp) algorithms, The approach involves embedding codewords into the design of fundamental signal processing algorithms such as digital filters and the DFT in such a way that proof of authorship can be retained, and, if required, easily identified. The techniques discussed can be adapted to protect other fundamental dsp algorithms such as convolution and correlation. The protection of IP via watermarking techniques is increasingly being applied at all levels of design. It is particularly advantageous if such techniques are applied at the highest abstraction levels in the design flow and if such techniques are applied at basic algorithm level, they become very difficult to detect at lower levels of system design.

关键词： dsp algorithms intellectual property system on chip VLSI design watermarking

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ARCHITECTURE-DRIVEN SYNTHESIS TECHNIQUES FOR VLSI IMPLEMENTATION OF dsp algorithms

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PROCEEDINGS OF THE IEEE 1990年第2期78卷 319-335页

作者： DEMAN, H CATTHOOR, F GOOSSENS, G VANHOOF, J VANMEERBERGEN, J NOTE, S HUISKEN, J PHILIPS RES LABS 5600 JA EINDHOVENNETHERLANDS INTERUNIV MICROELECTR CTR LAB B-3030 LOUVAINBELGIUM KATHOLIEKE UNIV LEUVEN INST ELEKTROTECHLOUVAINBELGIUM

The state of the art of compiling digital signal processing (dsp) algorithms into silicon is discussed. It is indicated how digital signal processing differs from numerical data processing, including the consequences for the synthesis tools. On the basis of a broad range of dsp applications, four classes of architectures are then distinguished to serve as templates for four different synthesis systems. Although each of these four silicon compilers is tuned to a specific class of applications in order to generate area-efficient chips, they all accept as input the same behavioral dsp specification. The four selected architectural styles are best characterized by hard-wired bit-serial data-paths, microcoded multiprocessors, cooperating bit-parallel data-paths, and regular arrays. The characteristics of the first three architectures are treated in more detail in a discussion of three different Cathedral synthesis environments for their respective design. A fourth Cathedral environment, aiming at the synthesis of regular arrays, is still in an early stage of development and is not discussed. The claims for the compilers are substantiated by typical designs

关键词： Cathedral synthesis environments dsp algorithms dsp chips layout VLSI VLSI implementation architectural styles architecture-driven synthesis techniques area-efficient chips behavioral dsp specification circuit layout CAD classes of architectures cooperating bit-parallel data-paths digital signal processing digital signal processing chips hard-wired bit-serial data-paths microcoded multiprocessors regular arrays silicon compilers silicon compiling synthesis tools

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MULTIPROCESSOR IMPLEMENTATION OF REAL-TIME dsp algorithms

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1995年第3期3卷 393-403页

作者： WANG, DJ HU, YH IEEE Department of Electrical and Computer Engineering University of Wisconsin

In this paper, we consider multiprocessor implementation of real-time recursive digital signal processing algorithms. The objective is to devise a periodic schedule, and a fully static task assignment scheme to meet the desired throughput rate while minimizing the number of processors. Toward this goal, we propose a notion called cutoff time, We prove that the minimum-processor schedule can be found within a finite time interval bounded by the cutoff time. As such the complexity of the scheduling algorithm and the allocation algorithm can be significantly reduced. Next, taking advantage of the cutoff time, we derive efficient heuristic algorithms which promise better performance and less computation complexity compared to other existing algorithms. Extensive benchmark examples are tested,which yield most encouraging results.

关键词： .Processors Implementation of Real-Time dsp algorithms

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Real-time Audio Effects with dsp algorithms and DirectSound 6

Real-time Audio Effects with DSP Algorithms and DirectSound

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6th International Conference on Electronics, Computers and Artificial Intelligence (ECAI)

作者： Anghelescu, Petre Angelescu, Stefan Ionita, Silviu Univ Pitesti Dept Elect Commun & Comp Pitesti Romania

ISBN: (纸本)9781479954797

This paper is focused on the software implementation of dsp oriented algorithms for different audio effects, like Echo, 3-Tap Echo, Vibrato, Tremolo and Chorus. The main contribution of this research consists in a software application which is able to process in real time the audio signals received from the electric guitar using PC sound card. In addition, the application also includes a digital filter class used for implementation of a low pass filter as well as other filter types, a tone generator and the options for storing the sound samples in a wav file. The application is written in C# language which uses DirectSound library in order to process the sound samples on a low level.

关键词： Digital audio effects dsp algorithms DirectSound Electric guitar

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Fast Fixed-Point Optimization of dsp algorithms

Fast Fixed-Point Optimization of DSP Algorithms

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18th IEEE/IFIP International Conference on VLSI and System-on-Chip

作者： Caffarena, Gabriel Carreras, Carlos Lopez, Juan A. Fernandez, Angel Univ San Pablo CEU Madrid 28668 Spain Univ Politecn Madrid E-28040 Madrid Spain

ISBN: (纸本)9781424464708

In this paper, a fixed-point quantization noise estimator aiming at Digital Signal Processing (dsp) algorithms is presented. The estimator enables significant reduction in the computation time required to perform complex word-length optimizations while providing a high accuracy. Affine Arithmetic (AA) is used to provide a Signal-to-Quantization Noise-Ratio (SQNR) estimation for differentiable non-linear algorithms with and without feedbacks. The estimation is based on the parameterization of the statistical properties of the noise at the output of fixed-point algorithms. This parameterization allows to relate the fixed-point formats of the signals with the output noise distribution by means of fast matrix operations. Thus, a fast estimation is achieved and the word-length optimization computation time is significantly reduced. The estimator is tested using a subset of non-linear algorithms such as vector operations, power computation IIR filter, adaptive filters, and channel equalizers. The Word-length optimization computation time is boosted by three orders of magnitude while keeping the average estimation error down to 6% for most cases.

关键词： dsp algorithms SQNR estimation affine arithmetic digital signal processing algorithms digital signal processing chips fast fixed-point optimization fast matrix operations fixed point arithmetic fixed-point quantization noise estimator matrix algebra noise statistical property nonlinear algorithms nonlinear estimation optimisation signal-to-quantization noise-ratio estimation word-length optimization computation time

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Address Satisfaction for Storage Files with Fifos or Stacks during Scheduling of dsp algorithms 00

Address Satisfaction for Storage Files with Fifos or Stacks ...

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Proceedings of the 13th symposium on Integrated circuits and systems design

作者： C. A. Alba Pinto K. van Eijk B. Mesman J. Jess

ISBN: (纸本)9780769508436

Tight data- and timing constraints are imposed by dsp applications. Also, the target processor architecture or the synthesized circuit template conform resource constraints. Additionally, instead of registers address-limited storage files with fifos or stacks are used. Continuing previous work on register file capacity satisfaction, this paper presents a method that during scheduling handles address constraints of storage files with fifos or stacks together with timing and resource constraints.

关键词： fifos target processor architecture digital signal processing chips synthesized circuit template processor scheduling bottleneck identification file organisation resource allocation address constraints dsp algorithms register file capacity storage allocation resource constraints stacks computer architecture storage management timing constraints storage files scheduling

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Ultra low phase noise dsp oscillator

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IEEE SIGNAL PROCESSING MAGAZINE 2007年第4期24卷 121-124页

作者： Harris, Fred San Diego State Univ San Diego CA 92182 USA

This article describes a novel complex oscillator, which is based on an interesting variation of the traditional CORDIC DDS and produces sine and cosine output samples of any specified angle. Our oscillator provides drastically improved phase noise performance (relative to a traditional CORDIC DDS) without the need for additional CORDIC iteration processing. In addition, our oscillator supports real-time output sample-by-sample digital frequency control. In describing our enhanced complex oscillator, we first present the arithmetic processing needed to generate sine and cosine samples. Next we show how that processing is implemented using the CORDIC algorithm. Then we detail the trick used to reduce oscillator phase noise errors. Finally we show how to guarantee a stable oscillator output amplitude and present an example of our oscillator\'s ultra low phase noise performance.

关键词： digital arithmetic direct digital synthesis oscillators signal processing CORDIC iterations dsp algorithms arithmetic- processing cosine output samples direct digital synthesizer oscillator phase noise error reduction real time output sample-by-sample di Digital arithmetic digital synthesizers signal processing direct digital synthesis Oscillators Low phase noise

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Performance of dsp-assisted gray-coded DP-16-QAM Nyquist-DWDM super-channel transceiver for high-speed long-haul optical interconnects

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PHOTONIC NETWORK COMMUNICATIONS 2023年第1期45卷 37-48页

作者： Kakati, Dhiman Sonkar, Ramesh Kumar Indian Inst Technol Guwahati Dept Elect & Elect Engn Gauhati 781039 India

In this paper, a 64-channel Nyquist-DWDM system has been proposed for spectral-efficient long-haul optical interconnects. Dual-polarization 16-QAM has been used at each transmitter, and the homodyne detection technique decodes the transmitted symbols at the receiver. Gray code used in the transmitters shows an improved OSNR tolerance, receiver sensitivity, and transmission distance in comparison to the differential code. Erbium-doped fiber amplifiers compensate for attenuation at regular intervals in the multi-span transmission line. Digital signal processing techniques with advanced algorithms compensate for the signal impairments after demodulation. The transceiver performance has been analyzed through comprehensive numerical methods for the 25 GHz and 50 GHz DWDM grids. The system performance has been optimized considering various parameters such as laser power, linewidth, crosstalk, OSNR tolerance, and receiver sensitivity. The transceiver achieves 7.68 Tbps data rate over a transmission distance of 3100 km and 2650 km for the considered DWDM grids, respectively. The gray-coded system possesses an OSNR tolerance of 16.4 dB and the overall DWDM system spectral efficiency of 4.71 b/s/Hz at its maximum transmission distance. This super-channel transceiver shall be helpful in high-capacity long-haul transmission and backbone support to the existing network infrastructure.

关键词： Nyquist-WDM Gray code dsp algorithms Coherent detection Super-channel transceiver

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Design and implementation of a reconfigurable architecture for dsp 5

Design and implementation of a reconfigurable architecture f...

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5th International Conference on ASIC

作者： Yang, Y Mao, ZG Lai, FC Zhao, B Xia, YF Harbin Inst Technol Ctr Microelect Harbin 150001 HeiLongJiang Peoples R China

ISBN: (纸本)078037889X

To accelerate the execution of most dsp(Digital Signal Processing) algorithms such as FFT, FIR, Vector operations, while keeping the flexibility of the chip, a reconfigurable architecture (named ReDAr) for dsp is proposed and implemented, and finally will be applied to the Radar system of Automatic Navigation Equipment. By analyzing these algorithms, the structure of Reconfigurable Processing Element (RPE), the Crossbar interconnect network, the Memory organization. the host controlling strategy, and the data sequencing scheme of the architecture are conceived. and parts of them, including the RPE, Crossbar. data sequencer, are reconfigurable. After configuration. it can be interconnected into a parallel and pipelined framework. closely matching the algorithms and like a dedicated hardware. By simulation. the performances of these algorithms mapped onto this architecture are comparative to algorithm-specific chips in market, and satisfy the requirement of the targeted application.

关键词： radar signal processing radionavigation reconfigurable architectures parallel processing pipeline processing fast Fourier transforms FIR filters ReDAr reconfigurable architecture dsp algorithms digital signal processing algorithms FFT fast Fourier transform FIR finite impulse response vector operations radar system automatic navigation equipment RPE reconfigurable processing element crossbar interconnect network memory organization data sequencing pipelined framework parallel framework

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