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Compiler-Assisted data Distribution and Network Configuration for Chip Multiprocessors

IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2012年第11期23卷 2058-2066页

作者： Li, Yong Abousamra, Ahmed Melhem, Rami Jones, Alex K. Univ Pittsburgh Comp Engn Program Pittsburgh PA 15261 USA Univ Pittsburgh Dept Comp Sci Pittsburgh PA 15260 USA

data access latency, a limiting factor in the performance of chip multiprocessors, grows significantly with the number of cores in nonuniform cache architectures with distributed cache banks. To mitigate this effect, we use a compiler-based approach to leverage data access locality, choose an optimized data placement and efficiently configure the on-chip network. The proposed experimental compiler framework employs novel compilation techniques to discover and represent multithreaded memory access patterns (MMAPs). At runtime, symbolic MMAPs are resolved and used by a partitioning algorithm to choose a partition of allocated memory blocks among the forked threads in the analyzed application. This partition is used to enforce data ownership by associating the data with the core that executes the thread owning the data. Based on the partition, the communication pattern of the application can be extracted. We demonstrate how this information can be used in an experimental architecture to accelerate applications. In particular, our compiler assisted data partitioning approach shows a 20 percent speedup over shared caching and 5 percent speedup over the closest runtime approximation, first touch. By leveraging the communication pattern we can achieve a comparable performance to a system that uses a complex centralized network configuration system at runtime. Thus, our final system saves significant runtime complexity and achieves an 5.1 percent additional speedup through the addition of the reconfigurable network.

关键词： Circuit switching network-on-chip communication data access pattern data partition

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CUDA-Zero:a framework for porting shared memory GPU applications to multi-GPUs

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Science China(Information Sciences) 2012年第3期55卷 663-676页

作者： CHEN DeHao , CHEN WenGuang & ZHENG WeiMin Department of Computer Science and Technology, Tsinghua University, Beijing 100084, China 1. Department of Computer Science and Technology Tsinghua University Beijing 100084 China

As the prevalence of general purpose computations on GPU, shared memory programming models were proposed to ease the pain of GPU programming. However, with the demanding needs of more intensive workloads, it’s desirable to port GPU programs to more scalable distributed memory environment, such as multi-GPUs. To achieve this, programs need to be re-written with mixed programming models (e.g. CUDA and message passing). Programmers not only need to work carefully on workload distribution, but also on scheduling mechanisms to ensure the efficiency of the execution. In this paper, we studied the possibilities of automating the process of parallelization to multi-GPUs. Starting from a GPU program written in shared memory model, our framework analyzes the access patterns of arrays in kernel functions to derive the data partition schemes. To acquire the access pattern, we proposed a 3-tiers approach: static analysis, profile based analysis and user annotation. Experiments show that most access patterns can be derived correctly by the first two tiers, which means that zero efforts are needed to port an existing application to distributed memory environment. We use our framework to parallelize several applications, and show that for certain kinds of applications, CUDA-Zero can achieve efficient parallelization in multi-GPU environment.

关键词： CUDA parallelization data access pattern multi-GPU

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Dynamic data Replication Scheme in the Cloud Computing Environment

Dynamic Data Replication Scheme in the Cloud Computing Envir...

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IEEE 2nd Symposium on Network Cloud Computing and Applications (NCCA)

作者： Jeon, Myunghoon Lim, Kwang-Ho Ahn, Hyun Lee, Byoung-Dai Kyonggi Univ Dept Comp Sci Suwon South Korea

ISBN: (纸本)9780769549439;9781467355810

In the cloud computing environment, data replication strategy (DRS) is used to improve data access. Related studies have proposed data replication strategies. The performances of these strategies are closely related to the users' access patterns, and work optimally for a particular data access pattern. However, as the data access patterns become more flexible and unpredictable, it is difficult to manage them with traditional replication strategies. Given this circumstance, this paper proposes an algorithm that detects changes in a user's data access pattern and dynamically applies an optimal replication strategy. The proposed algorithm has the advantage of maintaining an optimal performance by responding to various data access patterns. We tested the proposed algorithm and validated its effectiveness.

关键词： component Clouds data access pattern Dynamic Switching Replication

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A Tool for Characterizing and Succinctly Representing the data access patterns of Applications

A Tool for Characterizing and Succinctly Representing the Da...

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IEEE International Symposium on Workload Characterization (IISWC)

作者： Mills, Catherine Snavely, Allan Carrington, Laura Univ Calif San Diego Dept Comp Sci & Engn La Jolla CA 92093 USA San Diego Supercomp Ctr San Diego CA USA

ISBN: (纸本)9781457720642

Application address streams contain a wealth of information that can be used to characterize the behavior of applications. However, the collection and handling of address streams is complicated by their size and the cost of collecting them. We present PSnAP, a compression scheme specifically designed for capturing the fine-grained patterns that occur in well structured, memory intensive, high performance computing applications. PSnAP profiles are human readable and reveal a great deal of information about the application memory behavior. In addition to providing insight to application behavior the profiles can be used to replay a proxy synthetic address stream for analysis. We demonstrate that the synthetic address streams mimic very closely the behavior of the originals.

关键词： Arrays Benchmark testing Decoding High performance computing History Humans Instruments PSnAP address streams behavioural sciences computing compression scheme data access pattern data compression fine-grained pattern high performance computing human read

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Sparse triangular solves for ILU revisited: data layout crucial to better performance

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INTERNATIONAL JOURNAL OF HIGH PERFORMANCE COMPUTING APPLICATIONS 2011年第4期25卷 386-391页

作者： Smith, Barry Zhang, Hong IIT Dept Comp Sci Chicago IL 60616 USA Argonne Natl Lab Div Math & Comp Sci Argonne IL 60439 USA

A key to good processor utilization for sparse matrix computations is storing the data in the format that is most conducive to fast access by the memory system. In particular, for sparse matrix triangular solves the traditional compressed sparse matrix format is poor, and minor adjustments to the data structure can increase the processor utilization dramatically. Such adjustments involve storing the L and U factors separately and storing the U rows 'backwards' so that they are accessed in a simple streaming fashion during the triangular solves. Changes to the PETSc libraries to use this modified storage format resulted in over twice the floating-point rate for some matrices. This improvement can be accounted for by a decrease in the cache misses and TLB (transaction lookaside buffer) misses in the modified code.

关键词： sparse triangular solve ILU factorization matrix-vector product data access pattern data layout

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SPEEDING UP BEST NEIGHBORHOOD MATCHING ALGORITHM FOR HIGH-DEFINITION IMAGE ON GPU PLATFORM

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INTERNATIONAL JOURNAL OF IMAGE AND GRAPHICS 2011年第3期11卷 315-337页

作者： He, Liqiang Zhang, Guangyong Zhang, Yanyan Inner Mongolia Univ Coll Comp Sci Hohhot 010021 Inner Mongolia Peoples R China Inner Mongolia Univ Coll Comp Sci Comp architecture Hohhot 010021 Inner Mongolia Peoples R China Inner Mongolia Univ Coll Comp Sci Comp Sci & Comp architecture Hohhot 010021 Inner Mongolia Peoples R China

Error concealment restores the visual integrity of image content that has been damaged due to a bad network transmission. Best neighborhood matching (BNM) is an effective image-recovery method that exploits the information redundancy in a block-coded broken image to find similar content that it then uses to repair or conceal errors. On a high-definition image, BNM is traditionally implemented sequentially, which requires a relatively long time and thus is not suitable for real-time or high-volume use. In this paper, we analyze the data access patterns of the BNM algorithm, and exploit a graphics process unit (GPU) platform to speed up the execution through a parallel implementation. We compare and combine several different GPU optimization methods (coalesced global memory access, shared memory, register files, etc.), and propose an improvement to the parallel BNM algorithm. Experimental results show that our approach can speed up BNM 62 times over the sequential approach without any obvious loss of accuracy.

关键词： BNM CUDA data access pattern coalesced global memory access shared memory

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Exploiting the performance gains of modern disk drives by enhancing data locality

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INFORMATION SCIENCES 2009年第14期179卷 2494-2511页

作者： Deng, Yuhui Cambridge Cranfield High Performance Comp Facil Cranfield MK43 0AL Beds England

Due to the widening performance gap between RAM and disk drives, a large number of I/O optimization methods have been proposed and designed to alleviate the impact of this gap. One of the most effective approaches of improving disk access performance is enhancing data locality. This is because the method could increase the hit ratio of disk cache and reduce the seek time and rotational latency. Disk drives have experienced dramatic development since the first disk drive was announced in 1956. This paper investigates some important characteristics of modern disk drives. Based on the characteristics and the observation that data access on disk drives is highly skewed, the frequently accessed data blocks and the correlated data blocks are clustered into objects and moved to the outer zones of a modern disk drive. The idea attempts to enhance spatial locality, improve the efficiency of aggressive sequential prefetch, and take advantage of Zoned Bit Recording (ZBR). An experimental simulation is employed to investigate the performance gains generated by the enhanced data locality. The performance gains are analyzed by breaking down the disk access time into seek time, rotational latency, data transfer time, and hit ratio of the disk cache. Experimental results provide useful insights into the performance behaviours of a modern disk drive with enhanced data locality. (C) 2009 Elsevier Inc. All rights reserved.

关键词： Disk drive data locality data access pattern Block correlation data migration Performance

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EED: Energy Efficient Disk drive architecture

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INFORMATION SCIENCES 2008年第22期178卷 4403-4417页

作者： Deng, Yuhui Wang, Frank Na Helian Cranfield Univ Campus Cambridge Cranfield High Performance Comp Facil Ctr Grid Comp Cranfield MK43 0AL Beds England Univ Hertfordshire Dept Comp Sci Hatfield AL10 9AB Herts England

Energy efficiency has become one of the most important challenges in designing future computing systems, and the storage system is one of the largest energy consumers within them. This paper proposes an Energy Efficient Disk (EED) drive architecture which integrates a relatively small-sized NAND flash memory into a traditional disk drive to explore the impact of the flash memory on the performance and energy consumption of the disk. The EED monitors data access patterns and moves the frequently accessed data from the magnetic disk to the flash memory. Due to the data migration, most of the data accesses can be satisfied with the flash memory, which extends the idle period of the disk drive and enables the disk drive to stay in a low power state for an extended period of time. Because flash memory consumes considerably less energy and the read access is much faster than a magnetic disk, the EED can save significant amounts of energy while reducing the average response time. Real trace driven simulations are employed to validate the proposed disk drive architecture. An energy coefficient, which is the product of the average response time and the average energy consumption, is proposed as a performance metric to measure the EED. The simulation results, along with the energy coefficient, show that the EED can achieve an 89.11% energy consumption reduction and a 2.04% average response time reduction with cello99 trace, a 7.5% energy consumption reduction and a 45.15% average response time reduction with cello96 trace, and a 20.06% energy consumption reduction and a 6.02% average response time reduction with TPC-D trace, respectively. Traditionally, energy conservation and performance improvement are contradictory. The EED strikes a good balance between conserving energy and improving performance. (c) 2008 Elsevier Inc. All rights reserved.

关键词： Disk drive Energy efficiency data access pattern Architecture Non-volatile memory

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行动无线环境下相依资料广播之排程

行动无线环境下相依资料广播之排程

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作者：林昆锋国立台北科技大学

学位级别：硕士

在无线行动环境下，资料广播是一个对行动用户散布资讯的一个有效的方式。在一些应用里面，所有资料被存取的关系可以被表示成一个有方向性非回圈图(Directed Acyclic Graph, DAG)。在本论文里，我们探讨在无线环境下，对于有DAG这样... 详细信息

在无线行动环境下，资料广播是一个对行动用户散布资讯的一个有效的方式。在一些应用里面，所有资料被存取的关系可以被表示成一个有方向性非回圈图(Directed Acyclic Graph, DAG)。在本论文里，我们探讨在无线环境下，对于有DAG这样的存取关系，如何有效建置一个广播排程。在单一频道里，这样一个广播排程不仅最小化存取延迟时间而且满足DAG的线性顺序。最小化存取延迟时间保证了服务的品质(QoS)。我们证明寻找最佳广播排程是一个NP-hard问题并且提出一些探索式的方法。在分析并比较这些探索式的方法之延迟时间与时间复杂度之后，我们实践并比较他们的效率。另一方面，在多广播频道里，我们也证明寻找一个有最少的延迟时间且满足祖先性质（维持DAG相依性）的最佳之广播排程是一个NP-hard问题。我们更进一步指出在特定条件下，在线性时间内对于输入的DAG可以找出一个最佳的广播排程，并以此条件提出一个演算法产生最佳广播排程。然而对于一般的DAGs而言，我们提出一些探索式的演算法来产生广播排程，并且分析比较他们的效率。

关键词： latency broadcast NP-hard data access pattern DAG

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Code restructuring for improving cache performance of MPSoCs

Code restructuring for improving cache performance of MPSoCs

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IEEE/ACM International Conference on Computer Aided Design

作者： Chen, G Kandemir, M Penn State Univ Dept Comp Sci & Engn University Pk PA 16802 USA

ISBN: (纸本)078039254X

One of the critical goals in code optimization for MPSoC architectures is to minimize the number of off-chip memory accesses. This is because such accesses can be extremely costly from both performance and power angles, While conventional data locality optimization techniques can be us, for improving data access pattern of each processor independently, such techniques usually do not consider locality for shared data. This paper proposes a strategy, that reduces the number of off-chip references due to shared data. It achieves this goal by restructuring a parallelized application code in such a fashion that a given data block is accessed by parallel processors within the same time frame, so that its reuse is maximized while it is in the con-chip memory space. This tends to minimize the number of off-chip references since the accesses to a given data block are clustered within a short period of time during execution. Our approach employs a polyhedral tool that helps us isolate computations that manipulate a given data block.

关键词： cache storage circuit optimisation integrated circuit design microprocessor chips parallel processing system-on-chip MPSoC architectures cache performance code restructuring data access pattern data block data locality optimization techniques off-chip me Circuit optimization system-on-chip cache storage Microprocessor chips integrated circuit design PARALLEL PROCESSING (COMPUTERS) off-chip code optimization time frame concurrent processor

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