The first step was to settle one possible Basic Hardware Configuration for GANIL. Now work is going on to develop corresponding software. We present only a GENERAL OVERVIEW of GANIL first ACQUISITION SYSTEM G.A.S. wit...
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The first step was to settle one possible Basic Hardware Configuration for GANIL. Now work is going on to develop corresponding software. We present only a GENERAL OVERVIEW of GANIL first ACQUISITION SYSTEM G.A.S. with regard to its software design, definition and state : specialized micro-processor CAB-GANIL and associated DMA-DMI, graphic displays, acquisition monitor...
A performance-measurement facility for current leads has been developed as a part of Argonne National Laboratory's program to develop applications for high-temperature superconductors. The facility measures the ra...
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A performance-measurement facility for current leads has been developed as a part of Argonne National Laboratory's program to develop applications for high-temperature superconductors. The facility measures the rate of helium vapor boil-off due to current-lead heat input to liquid helium and the pressure drop across a current lead for a pair of leads operating at currents up to 100 A. The facility's major components are a liquid-helium dewar with low background-heat input;a dewar insert that incorporates the current leads and associated instrumentation or connections for flow, pressure, level, temperature and voltage measurements;and a computer driven data-acquisition system. Background heat input is low enough so that boil-off rates one-tenth that of an optimized conventional lead can be characterized. The facility has been operated with conventional (i.e., vapor-cooled copper) leads, and with leads incorporating high-temperature superconductors at their cold ends. Details of the facility design, construction, and operating experience are presented.
For more than a decade, the PAPI performance-monitoring library has provided a clear, portable interface to the hardware performance counters available on all modern CPUs and other components of interest (e.g., GPUs, ...
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ISBN:
(纸本)9781479955480
For more than a decade, the PAPI performance-monitoring library has provided a clear, portable interface to the hardware performance counters available on all modern CPUs and other components of interest (e.g., GPUs, network, and I/O systems). Most major end-user tools that application developers use to analyze the performance of their applications rely on PAPI to gain access to these performance counters. One of the critical roadblocks on the way to larger, more complex high performance systems, has been widely identified as being the energy efficiency constraints. With modern extreme scale machines having hundreds of thousands of cores, the ability to reduce power consumption for each CPU at the software level becomes critically important, both for economic and environmental reasons. In order for PAPI to continue playing its well established role in HPC, it is pressing to provide valuable performance data that not only originates from within the processing cores but also delivers insight into the power consumption of the system as a whole. An extensive effort has been made to extend the Performance API to support power monitoring capabilities for various platforms. This paper provides detailed information about three components that allow power monitoring on the Intel Xeon Phi and Blue Gene/Q. Furthermore, we discuss the integration of PAPI in PARSEC - a task-based dataflow-driven execution engine - enabling hardware performance counter and power monitoring at true task granularity.
We propose a dynamic scheduling approach for the concurrent execution of logical actor instances on a single synthesized actor instance. Based on a formal dataflow model of computation, the proposed approach can be ap...
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ISBN:
(纸本)9783981537024
We propose a dynamic scheduling approach for the concurrent execution of logical actor instances on a single synthesized actor instance. Based on a formal dataflow model of computation, the proposed approach can be applied to a wide range of applications in a model-based design flow. As case-study, we evaluate a bus-cycle-accurate SystemC RTL model based on an InfiniBand network adapter in a PCI Express system.
We describe a high-level design method to synthesize multi-phase regular arrays. The method is based on deriving component designs using classical regular (or systolic) array synthesis techniques and composing these s...
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ISBN:
(纸本)0769517129
We describe a high-level design method to synthesize multi-phase regular arrays. The method is based on deriving component designs using classical regular (or systolic) array synthesis techniques and composing these separately evolved component design into a unified global design. Similarity transformations are applied to component designs in the composition stage in order to align dataflow between the phases of the computations. Three transformations are considered: rotation, reflection and translation. The technique is aimed at the design of hardware components for high-throughput embedded systems applications and we demonstrate this by deriving a multi-phase regular array for the 2-D DCT algorithm which is widely used in many video communications applications.
Event triggers in colliding beam experiments are often based on the detection of apparent tracks in relatively broad pre-assigned "roads". The validity of the trigger is then verified by a filter program whi...
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Event triggers in colliding beam experiments are often based on the detection of apparent tracks in relatively broad pre-assigned "roads". The validity of the trigger is then verified by a filter program which accepts only those events which satisfy somewhat more stringent geometrical conditions. In high background experiments, a good deal of time is wasted while the filter program searches the list of wire addresses to find those that fall within the particular roads that produced the trigger, thus limiting the ability of the filter to keep up with high event rates. A hardware processor will be described that performs this correlation function in real time on the data stream flowing to the computer. A particular feature of this processor is its ability to work with cylindrical detectors where the roads may straddle the first chamber wire and thus may include both high-numbered and low-numbered addresses.
Logic state analyzers are used to monitor, or measure, the sequence of program and dataflow in sequential processors, such as computers and microprocessors, as a means of debugging, testing, and troubleshooting these...
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Logic state analyzers are used to monitor, or measure, the sequence of program and dataflow in sequential processors, such as computers and microprocessors, as a means of debugging, testing, and troubleshooting these processors. The application of these measurements is discussed using examples of debugging and troubleshooting techniques made possible by logic state analyzers. The capabilities required to implement these measurements are set forth using the previously described measurements. These measurement capabilities, then, become the functional definition of a logic state analyzer. Finally, the block diagram required to implement these measurement capabilities is developed as a further means of describing the measurement of logic or data sequences and the application of these measurements to troubleshooting, debugging, and testing sequential digital machines and systems.
A hierarchical machine-to-machine (M2M) communication network, where multiple heterogeneous devices compete for transmission on congested links, is considered. In such a network, the cluster headers gather the network...
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A hierarchical machine-to-machine (M2M) communication network, where multiple heterogeneous devices compete for transmission on congested links, is considered. In such a network, the cluster headers gather the network coding and routing messages from multiple M2M devices and forward them to the cellular network. We propose a novel discriminatory user-based utility mechanism for network coding users and routing users. The price of anarchy (PoA), which is used to characterize the worst-case efficiency bounds, is analyzed. The simulation results show that network coding could promote the efficiency to a certain extent.
Transistorized, high-speed, general-purpose digital computing equipment has been designed as the primary airborne real-time calculating element for the advanced bombing, navigation, and missile guidance subsystem inte...
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Transistorized, high-speed, general-purpose digital computing equipment has been designed as the primary airborne real-time calculating element for the advanced bombing, navigation, and missile guidance subsystem intended for use in the B-70 air vehicle. Because of the critical nature of this application, reliability, maintainability, and flexibility requirements received the utmost consideration in every design phase. Maximum reliability was achieved primarily through the use of a powerful, versatile, parallel main computer section supported by a minimal serial, emergency computer. A new approach to fault location enhances computer maintainability and permits in-flight repair, while flexibility is achieved by means of unique, high-speed input-output processing equipment.
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