In this paper, we introduce a new information flow model for trusted computing systems. Different from traditional system protection models, such as access control matrix model, this model analyze the information flow...
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ISBN:
(纸本)9780769530161
In this paper, we introduce a new information flow model for trusted computing systems. Different from traditional system protection models, such as access control matrix model, this model analyze the information flow in the system by tracing the operation sequences, and explains that the security status of a trusted computing system is the security attributes of information flows from input port to output port. With this model, we discuss the information channels in a trusted computing systems, and propose a "normal information-flow theorem" which gives a necessary condition of the existence of normal information flow.
Four examples of currently operating computer-communication networks are described in this tutorial paper. They include the TYMNET network, the GE Information Services network, the NASDAQ over-the-counter stock-quotat...
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Four examples of currently operating computer-communication networks are described in this tutorial paper. They include the TYMNET network, the GE Information Services network, the NASDAQ over-the-counter stock-quotation system, and the Computer Sciences Infonet. These networks all use programmable concentrators for combining a multiplicity of terminals. Included in the discussion for each network is a description of the overall network structure, the handling and transmission of messages, communication requirements, routing and reliability consideration where applicable, operating data and design specifications where available, and unique design features in the area of computer communications.
Memory cost is responsible for a large amount of the chip and/or board area of customized video and image processing system realizations. In this paper, we present a novel technique-founded on data-flow analysis-which...
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Memory cost is responsible for a large amount of the chip and/or board area of customized video and image processing system realizations. In this paper, we present a novel technique-founded on data-flow analysis-which allows to address the problem of background memory size evaluation for a given nonprocedural algorithm specification, operating on multidimensional signals with affine indexes. Most of the target applications are characterized by a huge number of signals, so a new polyhedral data-how model operating on groups of scalar signals is proposed. These groups are obtained by a novel analytical partitioning technique, allowing to select a desired granularity, depending on the application complexity. The method incorporates a way to tradeoff memory size with computational and controller complexity.
We describe here the FB [ 1 ] double port buffer memory developped at the LPNHE of the University Paris VI. Its purposes are to make available same features useful in the High Energy environment, to reduce, for a give...
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We describe here the FB [ 1 ] double port buffer memory developped at the LPNHE of the University Paris VI. Its purposes are to make available same features useful in the High Energy environment, to reduce, for a given amount of memory, the dead time data collection in a large size (in term of read-out channels) High Energy experiment and to get a buffer of memory as cheap and reliable as possible. The FB protocol, on the crate and cable side, is exploited using the coupler on 4 PAL's developped by G. Fremont [ 2 ] and E. Sanchis. The data-Space is divided in 4 independent smaller blocks in a way such that a block can be accessed from a port while a different block is accessed from the other port. The two ports are : A, the FB crate port and B, the FB cable port. The buffer works as a rotary FIFO, looping over the 4 blocks of memory, but allowing for any random access. A mechanism is implemented on the board in order to be able to link different modules placed everywhere. If there are m modules, the looping will be around m*4 memory blocks. A multi event function is implemented on the board. HFB is quiped of two NTA for the dataSpace on the port "A", and a flag to choose between them, to allow for a FB spying of data during the DAS dead time.
This paper describes and demonstrates a toolchain which enables HW-SW co-synthesis from a single high-level dataflow program. This toolchain does not only enable rapid-prototyping of complex designs, but also provides...
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ISBN:
(纸本)9781467357623;9781467357609
This paper describes and demonstrates a toolchain which enables HW-SW co-synthesis from a single high-level dataflow program. This toolchain does not only enable rapid-prototyping of complex designs, but also provides a complete system integration framework including synthesis of SW-HW interconnect. This framework minimizes the designer efforts for a low level implementation. A co-design example of a JPEG codec is demonstrated using a high-level dataflow language, named CAL.
Recently substantial research has been devoted to Unmanned Aerial Vehicles (UAVs). One of a UAV's most demanding subsystem is vision. The vision subsystem must dynamically combine different algorithms as the UAV&#...
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ISBN:
(纸本)0769517919
Recently substantial research has been devoted to Unmanned Aerial Vehicles (UAVs). One of a UAV's most demanding subsystem is vision. The vision subsystem must dynamically combine different algorithms as the UAV's goal and surrounding chang. To fully utilize the available hardware, a run time system must be able to vary the quality and the size of regions the algorithms are applied to, as the number of image processing tasks changes. To allow this the run time system and the underlying computational model must be integrated. In this paper we present a computational model suitable for integration with a run time system. The computational model is called Image Processing dataflow Graph (IP-DFG). IP-DFG has been developed for modeling of complex image processing algorithms. IP-DFG is based on dataflow graphs, but has been extended with hierarchy and new rules for token consumption, which makes the computational model more flexible and more suitable for human interaction. In this paper we also show that IP-DFGs are suitable for modelling expressions, including data dependent decisions and iterations, which are common in complex image processing algorithms.
This paper studies how processor failures affect the dataflow of the Level 1 Trigger in the BTeV experiment proposed to run at Fermilab's Tevatron. The failure analysis is crucial for a system with over 2500 proce...
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This paper studies how processor failures affect the dataflow of the Level 1 Trigger in the BTeV experiment proposed to run at Fermilab's Tevatron. The failure analysis is crucial for a system with over 2500 processing nodes and a number of storage units and communication links of the same order of magnitude. This paper is based on models of the L1 Trigger architecture and shows the dynamics of the architecture's dataflow. The dataflow analysis provides insight into how system variables are affected by single component failures and provides key information to the implementation of error recovery strategies. The analysis includes both short-term failures from which the system can recover quickly and long-term failures which imply a more drastic error-recovery strategy. The modeling results are supported by behavioral simulations of the Ll Trigger processing BTeV's GEANT Monte Carlo data.
A caller must satisfy the callee's precondition-that is, reach a state in which the callee may be called. Preconditions describe the state that needs to be reached, but not how to reach it. We combine static analy...
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ISBN:
(纸本)9780769538914
A caller must satisfy the callee's precondition-that is, reach a state in which the callee may be called. Preconditions describe the state that needs to be reached, but not how to reach it. We combine static analysis with model checking to mine Computation Tree Logic (CTL) formulas that describe the operations a parameter goes through: "In parseProperties (String xml), the parameter xml normally stems from getProperties()." Such operational preconditions can be learned from program code, and the code can be checked for their violations. Applied to ASPECTJ, our TIKANGA prototype found 189 violations of operational preconditions, uncovering 9 unique defects and 36 unique code smells-with 44% true positives in the 50 top-ranked violations.
Stream processing has emerged as an important model of computation in the context of multimedia and communication sub-systems of embedded System-on-Chip (SoC) architectures. The dataflow nature of streaming applicatio...
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ISBN:
(纸本)9781479963072
Stream processing has emerged as an important model of computation in the context of multimedia and communication sub-systems of embedded System-on-Chip (SoC) architectures. The dataflow nature of streaming applications allows them to be most naturally expressed as a set of kernels iteratively operating on continuous streams of data. The kernels are computationally intensive and exhibit large amounts of data and instruction level parallelism. Streaming applications are mainly characterized by real-time constraints that demand high throughput and data bandwidth with limited global data reuse. Conventional architectures fail to meet these demands due to their poorly matched execution models and the overheads associated with instruction and data movements. We present StreamEngine, an embedded architecture for energy-efficient computation of stream kernels. StreamEngine introduces an instruction locking mechanism that exploits the iterative nature of the kernels and enables fine-grain instruction reuse. We also adopt a Context-aware dataflow Execution model to exploit instruction-level and data-level parallelism within the stream kernels. Each instruction in StreamEngine is locked to a Reservation Station and maintains a context that is updated upon execution;thus instructions never retire from the RS. The entire kernel is hosted in RS Banks close to functional units for energy-efficient instruction and operand delivery. We evaluate the performance and energy-efficiency of our architecture for stream kernel benchmarks by implementing the architecture with TSMC 45nm process, and comparison with an embedded RISC processor.
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