In this paper we present an interactive texture-based technique for visualizing three-dimensional vector fields. The goal of the algorithm is to provide a general volume rendering framework allowing the user to comput...
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In this paper we present an interactive texture-based technique for visualizing three-dimensional vector fields. The goal of the algorithm is to provide a general volume rendering framework allowing the user to compute three-dimensional flow textures interactively, and to modify the appearance of the visualization on the fly. To achieve our goal, we decouple the visualization pipeline into two disjoint stages. First, streamlines are generated from the 3D vector data. Various geometric properties of the streamlines are extracted and converted into a volumetric form using a hardware-assisted slice sweeping algorithm. In the second phase of the algorithm, the attributes stored in the volume are used as texture coordinates to look up an appearance texture to generate both informative and aesthetic representations of the underlying vector field. Users can change the input textures and instantaneously visualize the rendering results. With our algorithm, visualizations with enhanced structural perception using various visual cues can be rendered in real time. A myriad of existing geometry-based and texture-based visualization techniques can also be emulated.
One of the reasons that topological methods have a limited popularity for the visualization of complex 3D flow fields is the fact that such topological structures contain a number of separating stream surfaces. Since ...
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One of the reasons that topological methods have a limited popularity for the visualization of complex 3D flow fields is the fact that such topological structures contain a number of separating stream surfaces. Since these stream surfaces tend to hide each other as well as other topological features, for complex 3D topologies the visualizations become cluttered and hardly interpretable. This paper proposes to use particular stream lines called saddle connectors instead of separating stream surfaces and to depict single surfaces only on user demand. We discuss properties and computational issues of saddle connectors and apply these methods to complex flowdata. We show that the use of saddle connectors makes topological skeletons available as a valuable visualization tool even for topologically complex 3D flowdata.
In this paper, we present a simulation and architectural analysis technique of embedded DSP systems modeled using the MASIC methodology. MASIC is a grammar based methodology, which clearly separates the communication ...
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In this paper, we present a simulation and architectural analysis technique of embedded DSP systems modeled using the MASIC methodology. MASIC is a grammar based methodology, which clearly separates the communication from the computation part of the model and begins with an abstract level of modeling. Computations in embedded blocks are carried out using C functions and the flow of data among the blocks is expressed by the communication protocol written in the MASIC grammar description. Later, the abstract model is refined to a cycle true model. Different architectural decisions, like the bus architecture or the memory organization added during the refinement process, significantly affect the system performance. We use a Petri net based approach that provides the necessary synchronization to perform co-simulation and helps to evaluate the effects of architectural decisions. The correctness of the protocol description is verified using Petri net based boundedness and conservation analysis.
Active networks represent a new approach to network architecture. Active networks provide a much more flexible network infrastructure than traditional networks do. Flexibility is a powerful merit of active networks, b...
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Active networks represent a new approach to network architecture. Active networks provide a much more flexible network infrastructure than traditional networks do. Flexibility is a powerful merit of active networks, but it can raise considerable security problems. Current active network researches have applied diverse techniques to solve them. Cryptography is one way of protecting active networks. However it should not be applied conventionally, since the active network paradigm is different from the traditional one. It means that, in active network environments, active packets containing programmable codes should perform computations at intermediate-nodes as well as end-nodes. That is, since the packet sending-node does not know the intermediate receiving-node, it cannot apply traditional cryptographic techniques that can process each other only between end-nodes. The paper proposes a secure method for transferring active packets and performing computations using a transformed digital signature schemes with message recovery, in an active network environment in which intermediate packet receiving-nodes are not fixed. The proposed scheme uses a modified public key digital signature scheme in which signing/verifying key pairs have almost the same bit length and the verification-key storing server plays the role of key management server.
We present an algorithm based on dynamic programming to perform the HW/SW partitioning and scheduling of a given task graph for minimum latency subject to resource constraint. The major contribution of this paper is t...
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We present an algorithm based on dynamic programming to perform the HW/SW partitioning and scheduling of a given task graph for minimum latency subject to resource constraint. The major contribution of this paper is to consider the edge communication delays in the dynamic programming solution of the problem. The algorithm has a polynomial run time complexity on trees. We also introduce a pruning technique to reduce the runtime of the worst-case scenario of directed acyclic graphs (DAGs). The algorithm has been implemented and the results are reported. A very fast quality heuristic is also proposed and implemented to provide good solutions in negligible run time.
Many embedded systems use a simple pipelined RISC processor for computation and an on-chip SRAM for data storage. We present an enhancement called Intelligent SRAM (ISRAM) that consists of a small computation unit wit...
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ISBN:
(纸本)9781581136883
Many embedded systems use a simple pipelined RISC processor for computation and an on-chip SRAM for data storage. We present an enhancement called Intelligent SRAM (ISRAM) that consists of a small computation unit with an accumulator that is placed near the on-chip SRAM. The computation unit can perform operations on two words from the same SRAM row or on one word from the SRAM and the other from the accumulator. This ISRAM enhancement requires only a few additional instructions to support the computation unit. We present a computation partitioning algorithm that assigns the computations to the processor or to the new computation unit for a given dataflow graph of a program. Performance improvement results from the reduction in the number of accesses to the SRAM, the number of instructions, and the number of pipeline stalls compared to the same operations in the processor. Experimental results on various benchmarks show up to 1.46X speedup with our enhancement.
This paper proposes a framework to support the development and use of tools that support the teaching of software and Web engineering. It describes the evolution of tools to support the teaching of software engineerin...
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This paper proposes a framework to support the development and use of tools that support the teaching of software and Web engineering. It describes the evolution of tools to support the teaching of software engineering from simple client-side tools that support drawing DFDs and UML diagrams to Web-based repositories that support process modelling. The paper specifically introduces the concept of "automated walkthroughs" and describes their use within the WWW. It also describes tools that automatically create automated walkthroughs for the World Wide Web (WWW) and their evaluation within a masters-level software engineering module. Conclusions are drawn about the general applicability of the framework and proposals are made for further work in this area.
We propose a set of extensions to the OpenMP programming model to express point-to-point synchronisation schemes. This is accomplished by defining, in the form of directives, precedence relations among the tasks that ...
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We propose a set of extensions to the OpenMP programming model to express point-to-point synchronisation schemes. This is accomplished by defining, in the form of directives, precedence relations among the tasks that are originated from OpenMP work-sharing constructs. The proposal is based on the definition of a name space that identifies the work parceled out by these work-sharing constructs. Then the programmer defines the precedence relations using this name space. This relieves the programmer from the burden of defining complex synchronization data structures and the insertion of explicit synchronization actions in the program that make the program difficult to understand and maintain. We briefly describe the main aspects of the runtime implementation required to support precedence relations in OpenMP. We focus on the evaluation of the proposal through its use two benchmarks: NAS LU and ASCI Seep3d
The paper outlines the key issues and fundamentals of morphware as a discipline of its own, and, as part of modern computing sciences. It discusses what is needed for the breakthrough.
The paper outlines the key issues and fundamentals of morphware as a discipline of its own, and, as part of modern computing sciences. It discusses what is needed for the breakthrough.
We present an algorithmic analog-to-digital converter (ADC) architecture for large-scale parallel quantization of internally analog variables in externally digital array processors. The converter quantizes and accumul...
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We present an algorithmic analog-to-digital converter (ADC) architecture for large-scale parallel quantization of internally analog variables in externally digital array processors. The converter quantizes and accumulates a binary weighted sequence of partial binary-binary matrix-vector products computed on the analog array, under presentation of bit-serial inputs in descending binary order. The architecture combines algorithmic conversion of the residue, as in a standard algorithmic ADC, with synchronous accumulation of the partial products from the array. In conjunction with row-parallel digital storage of matrix elements in the array, two pipelined architectures are presented to accumulate partial products with common binary weight across rows: row-parallel ADC with digital post-accumulation, and row-cumulative ADC with analog pre-accumulation. Simulation results are presented to quantify the trade-off in precision and area for full-parallel flash, and row-parallel and row-cumulative partial algorithmic, analog-to-digital conversion on the array.
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