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检索条件"主题词=Data Flow Computing"

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A data flow architecture for parallel computation

A data flow architecture for parallel computation

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International Conference on databases, Parallel Architectures and Their Applications

作者： P. Abellard G. Nolibe N. Razafindrakoto Laboratoire LAIAT University of Toulon La Garde France Le Galaxie B SBS TRIO Toulon France CNRIT Antananarivo Madagascar

A qualitative description and a mathematical definition of the data-flow Petri-net model are presented. The data-flow Petri nets are used for the data-flow multiprocessor operation. They can advantageously replace flow graphs for validation, simulation, and scheduling. In the functional assembler language used, the source program describes the function to be processed and does not specify all the steps as do classical assemblers. An application for the control of a telemanipulator robot with image processing is given.< >

关键词： Computer architecture Concurrent computing data flow computing Robotic assembly Mathematical model Petri nets flow graphs Computational modeling Processor scheduling Robots

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Sorting Packets by Packet Schedulers Using a Connected Trie data Structure

Sorting Packets by Packet Schedulers Using a Connected Trie ...

引用

IEEE Annual Joint Conference: INFOCOM, IEEE Computer and Communications Societies

作者： M. E. Kounavis A. Kumar R. Yavatkar Intel Corporation USA

Packet scheduling is a critical component of router data paths because it allows routers to divide bandwidth intelligently between competing flows. A large number of scheduling algorithms annotate packets with time stamps and subsequently sort these packets according to their annotated time stamp values. For these algorithms the problems of efficiently tagging and sorting packets are still open to investigation. In this paper we propose a data structure and algorithm that reduces the latency of determining the packet with the smallest time stamp to a single memory access time and a small constant number of computation steps, independent of the number of flows serviced by the scheduler. The complexity of inserting a packet into our sorting data structure is logarithmic as a function of the ratio between the maximum packet size and minimum connection weight. The latency of inserting a packet can be hidden by performing insertions of several packets in parallel. This is the fastest sorting data structure known to us. One of the most efficient alternative implementation techniques proposed by Chao et. al. [20] is associated with logarithmic complexity of the scheduling decision time, as a function of the maximum value of packet time stamps. Our solution applies to many different packet fair queuing algorithms including Weighted Fair Queuing [28], Self-Clocked Fair Queuing (SCFQ) [28] and Start Time Fair Queuing [4].

关键词： Sorting Scheduling algorithm data structures Delay Processor scheduling Bandwidth Costs data flow computing Communications Society USA Councils

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Operators matching in dynamic data flow architectures

Operators matching in dynamic data flow architectures

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International Conference on Computational Cybernetics (ICCC)

作者： L. Vokorokos N. Adam S. Petrik Department of Computers and Informatics Technical University of Košice Kosice Slovakia

Dynamic data flow system is a group of interconnected data flow driven processor elements, solving one compound task. data flow systems are systems driven by flow of data, effectively using natural parallelism rising during processing of large amount of data, for example: image processing, sound processing etc. Speed of dynamic data flow system depends on used interconnection network, suitability of parallel architecture usage and also on control of operands matching process. This article deals with operands matching process control optimization. There is a design of part of coordinating processor, controlling operands matching process, described in this article

关键词： Computer architecture Computer aided instruction Concurrent computing data flow computing High performance computing Neurons Parallel processing Control systems Process control Computer networks

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Designing new programming constructs in a data flow VL

Designing new programming constructs in a data flow VL

引用

IEEE Symposium on Visual Languages

作者： E. Ghittori M. Mosconi M. Porta Dipartimento di Informatica e Sistemistica University di Pavia Pavia Italy

A powerful and useful data-flow Visual Programming Language (DFVPL) must provide the necessary programming constructs to deal with complex problems. The main purpose of this paper is to give a contribution to the deba... 详细信息

关键词： Computer languages Lighting control data flow computing Computational modeling Libraries Control systems Programming profession Usability Sequential analysis data structures

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Nets and data flow interpreters

Nets and data flow interpreters

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Annual Symposium on Logic in Computer Science

作者： A. Rabinovich B.A. Trakhtenbrot School of Mathematical Sciences Raymond and Beverly Sackler Faculty of Exact Sciences Tel-Aviv University Tel-Aviv Israel

The authors investigate and compare two ways of specifying stream relations (in particular, stream functions). The first uses relational programs, i.e., netlike program schemes in which the signature primitives are interpreted as relations over a given CPO. No stream domains are assumed; semantics is in fixed-point style. The second is through data flow nets, i.e., nets whose nodes are interpreted as processes (computational stations). The authors prove the existence of an adequate data flow interpreter for relational programs over all relations and its uniqueness. When dealing with functions the interpreter is modular and obeys the Kahn principle, the authors identify two kinds of anomalies. The first (meagerness anomaly) is caused by the defect of the used processes (computational stations) and holds in fact for arbitrary input-output behaviors. The second (ambiguity anomaly) is rooted in the semantics of relational nets over arbitrary CPO. It is unavoidable in any extension beyond functional behaviors.< >

关键词： Computer networks data flow computing Functional programming Equations flow graphs Parallel processing Concurrent computing

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Rate-optimal static scheduling of DSP data flow graphs onto multiprocessors using circuit contraction

Rate-optimal static scheduling of DSP data flow graphs onto ...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： A. Shatnawi M.O. Ahmad M.N.S. Swamy Department of Electrical and Computer Engineering Concordia University Montreal QUE Canada Department of Electrical and Computer Engzneering Concordia University Montreal QUE Canada Department of Electrical Engineering City University of New York New York NY USA

This paper is concerned with the compile-time (static) scheduling of data flow graphs (DFGs) onto multiprocessor systems. It mainly concentrates on producing a rate-optimal time schedule that achieves the minimum iteration period, known as the iteration period bound. A combinatorial theory is developed to produce a rate-optimal time schedule for a fully specified DFG. The DFG is first converted to a critical graph by making all its circuits critical. Next, it is transformed into an acyclic graph through a sequence of circuit contractions. An algorithm is then proposed which achieves the time scheduling of the given DFG by first scheduling the acyclic graph, followed by a scheduling of the critical circuits in an order which is reverse to that of their contraction.

关键词： Digital signal processing flow graphs Circuits Processor scheduling Signal processing algorithms Application software Delay IIR filters data flow computing Scheduling algorithm

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Simulation of a data flow computer

Simulation of a data flow computer

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ACE. Proceedings of [Annual Convention and Exhibition of the IEEE In India]

作者： N.K. Jog Softek Private Limited New Delhi India

A data flow computer architecture achieves hitgher computing speeds than the traditional von Newmann architecture by exploiting software parallelism at the instruction level in a highly parallel system of processing hardware. data flow architectures executs- data flow graphs - directed graphs in which nodes represent instructions and interconnecting arcs define data flow oaths. One such data flow architecture, the Manchester data flow Computer has several rings which communicate via a common switch. This pacer describes the simulation of a single such ring. The code is written in Modula-2 using object oriented techniques. Partial cerformance figures obtained by the author's group are also presented. The paper concludes by suggesting several simulator enhancements.

关键词： Computational modeling Computer simulation data flow computing Switches Computer architecture Hardware Centralized control flow graphs Parallel processing data visualization

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Lower bounds on the iteration time and the number of resources for functional pipelined data flow graphs

Lower bounds on the iteration time and the number of resourc...

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IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Y. Hu A. Ghouse B.S. Carlson The Advanced IC Design and Simulation Laboratory and the Department of Electrical Engineering State University of New York Stony Brook NY USA

An algorithm is presented to determine two lower bounds in functional pipelined data path synthesis. Given an iteration time constraint and a task initiation latency, the algorithm computes a lower bound on the number of functional units required to execute the data flow graph (DFG) of a loop body, and given a resource constraint and a task initiation latency the algorithm computes a lower bound on the number of time steps required to execute the DFG. The lower bounds not only greatly reduce the size of the solution space, but also provide a means to measure the proximity of the final solution to an optimal one. The bounds are computed in polynomial time; therefore the algorithm is very effective, especially for large DFGs. Experiments indicate that the lower bound is very tight. For all of the test cases the difference between our solution and the optimal solution is not greater than one.< >

关键词： flow graphs data flow computing Scheduling algorithm Optimal scheduling Integrated circuit synthesis Polynomials Pipeline processing Time factors Delay Algorithm design and analysis

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Silicon Compilation and Test for dataflow Implementations in GasP and Click

Silicon Compilation and Test for Dataflow Implementations in...

引用

作者： Mettala Gilla, Swetha Portland State University

学位级别：Ph.D.

Many modern computer systems are distributed over space. Well-known examples are the Internet of Things and IBM's TrueNorth for deep learning applications. At the Asynchronous Research Center (ARC) at Portland State University we build distributed hardware systems using self-timed computation and delay-insensitive communication. Where appropriate, self-timed hardware operations can reduce average and peak power, energy, latency, and electromagnetic interference. Alternatively, self-timed operations can increase throughput, tolerance to delay variations, scalability, and manufacturability. The design of complex hardware systems requires design automation and support for test, debug, and product characterization. This thesis focuses on design compilation and test support for dataflow applications. Both parts are necessary to go from self-timed circuits to large-scale hardware systems. As part of the research in design compilation, the ARCwelder compiler designed by Willem Mallon (previously with NXP and Philips Handshake Solutions) was extended. The key to testing distributed systems, including self-timed systems, is to identify the actions in the systems. In distributed systems there is no such thing as a global action. To test, debug, characterize, and even initialize distributed systems, it is necessary to control the local actions. The designs developed at the ARC separate the actions from the states. As part of the research in test and debug, a special circuit to control actions, called MrGO, was implemented. A scan and JTAG test interface was also implemented. The test implementations have been built into two silicon test experiments, called Weaver and Anvil, and were used successfully for testing, debug, and performance characterizations.

关键词： data flow computing Electrical engineering Integrated circuits Asynchronous circuits

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Cluster-oriented scheduling in pipelined data path synthesis

Cluster-oriented scheduling in pipelined data path synthesis

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IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： C.-T. Chang K. Rose R.A. Walker Center for Integrated Elecironics Rensselaer Polytechnic Institute Troy USA Center for Integrated Elecironics Department of Computer Science Rensselaer Polytechnic Institute Troy USA

We present a new algorithm for cluster-oriented scheduling (COS) in pipelined data path synthesis. First, cluster structure information is extracted from the corresponding linear graph representation of a data flow graph (DFG). Then, scheduling and allocation globally interact with the cluster information under the timing constraints of pipeline latency and data initialization interval (DII). Using this technique, the costs of registers, multiplexors, and interconnection were reduced dramatically in both the FIR and elliptic filter examples.< >

关键词： Job shop scheduling Processor scheduling Hardware data flow computing Clustering algorithms Scheduling algorithm flow graphs Pipelines High level synthesis Laboratories

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