Efficient use of machine resources in high-performance computer systems requires highly optimizing compilers with sophisticated analyses. Static analysis often fails to identify frequently executed portions of a progr...
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ISBN:
(纸本)0769516203
Efficient use of machine resources in high-performance computer systems requires highly optimizing compilers with sophisticated analyses. Static analysis often fails to identify frequently executed portions of a program which are the places where optimizations achieve the greatest benefit. This paper introduces a novel dataflow frequency analysis framework that computes the frequency with which a dataflow fact will hold at some program point based on profiling information. Several approaches which approximate the frequencies based on k-edge profiling have been presented. However, no feasible approach for obtaining the accurate solution exists so far. Recently, efficient techniques for recording whole program paths (WPPs) have been developed. Our approach for computingdataflow frequencies results in an accurate solution and utilizes WPPs to obtain the solution it? reasonable time. In our experiments we show that the execution time of WPP-based frequeny, analysis is in case of the SPEC benchmark suite only a fraction of the overall compilation time.
Gateways between IP-based networks and fieldbus systems often create the impression of providing a unique, standardised remote access to automation systems. At second sight, however, it becomes apparent that there are...
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ISBN:
(纸本)0780375866
Gateways between IP-based networks and fieldbus systems often create the impression of providing a unique, standardised remote access to automation systems. At second sight, however, it becomes apparent that there are several possibilities on the LAN side with individual strengths and shortcomings. This paper reviews typical functions expected from a fieldbus gateway and investigates the properties of SNMP, LDAP, SQL, HTTP and a specially designed proprietary protocol (IGUANA) with respect to their appropriateness for remote access. Particular emphasis is laid on the restriction these protocols impose on the way the data inside the gateway are structured. We find that none of these approaches fully satisfies all requirements.
Research has shown that precomputation microthreads can be useful for improving branch prediction and prefetching. However it is not obvious how to provide the necessary microarchitectural support, and few details hav...
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ISBN:
(纸本)0769518591
Research has shown that precomputation microthreads can be useful for improving branch prediction and prefetching. However it is not obvious how to provide the necessary microarchitectural support, and few details have been given in the literature. By judiciously constraining microthreads, we can easily adapt a superscalar machine to support many simultaneous microthreads. The nature of precomputation microthreads also requires efficient usage of resources. Our proposed implementation addresses this issue by dynamically identifying and aborting useless microthreads.
Active networks allow their users to inject customized programs into the nodes of the network. An extreme case, in which we are most interested, replaces packets with "capsules" - program fragments that are ...
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ISBN:
(纸本)0769515649
Active networks allow their users to inject customized programs into the nodes of the network. An extreme case, in which we are most interested, replaces packets with "capsules" - program fragments that are executed at each network router/switch they traverse. Active architectures permit a massive increase in the sophistication of the computation that is performed within the network. They will enable new applications, especially those based on application-specific multicast, information fusion, and other services that leverage network-based computation and storage. Furthermore, they will accelerate the pace of innovation by decoupling network services from the underlying hardware and allowing new services to be loaded into the infrastructure on demand. In this paper, we describe our vision of an active network architecture, outline our approach to its design, and survey the technologies that can be brought to bear on its implementation. We propose that the research community mount a joint effort to develop and deploy a wide area ActiveNet.
This paper aims to device an architecture which uses the capability of asynchronous concurrency of the dataflow architecture as well as spatial parallelism of SIMD machines for a class of image processing application...
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This paper aims to device an architecture which uses the capability of asynchronous concurrency of the dataflow architecture as well as spatial parallelism of SIMD machines for a class of image processing applications using reconfigurable processing elements (RPE). Overall processing speed is enhanced by: (a) concurrent functioning of the RPE; and (b) replacing software execution of signal processing functions by hardware approach using FPGA as RPE. Thus, a hybrid architecture, which functions as a dataflow machine at a functional level and exploits the capability of spatial parallelism by incorporating modified SIMD concepts is presented.
An approach for reconstruction of sparse high-resolution data from lower-resolution dense spatiotemporal data is introduced. The basic idea is to compute the dense feature velocities from lower-resolution data and pro...
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ISBN:
(纸本)076951695X
An approach for reconstruction of sparse high-resolution data from lower-resolution dense spatiotemporal data is introduced. The basic idea is to compute the dense feature velocities from lower-resolution data and project them to the corresponding high-resolution data for computing the missing data. In this context, the basic flow equation is solved for intensity, as opposed to feature velocities at high resolution. Although the proposed technique is generic, we have applied our approach to sea surface temperature (SST) data at 18 km (low-resolution dense data)for computing the feature velocities and at 4 km (high-resolution sparse data) for interpolating the missing data. At low resolution, computation of flow field is regularized and uses the incompressibility constraints for tracking fluid motion. At high resolution, computation of intensity is regularized for continuity across multiple frames.
Due to the abstract characteristics of "time", it's not hard for teachers to elucidate the concept practically, but it is also hard for children to understand clearly the meaning of this term, although i...
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ISBN:
(纸本)0769515096
Due to the abstract characteristics of "time", it's not hard for teachers to elucidate the concept practically, but it is also hard for children to understand clearly the meaning of this term, although it is such a common lexis in daily life. "Mindtools" is the concept developed for this; "using computers as Mindtools" means using computers as a facilitative tool to enhance the effects of learning knowledge. This study, based on the learning theory, applying the concept of "using computers as Mindtools" aims to subserve the teachers' teaching and students' learning in the elementary school. The result in this study shows that it can increase students' interest and motif in learning the concept of "time" in math when the computer is used as Mindtools.
Experimental single event upset characterization of the Pentium/sup /spl reg// 4, Pentium/sup /spl reg// III and Low Power Pentium/sup /spl reg// MMX microprocessors using proton irradiation is presented. Results are ...
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Experimental single event upset characterization of the Pentium/sup /spl reg// 4, Pentium/sup /spl reg// III and Low Power Pentium/sup /spl reg// MMX microprocessors using proton irradiation is presented. Results are compared with previous tests on other Pentium/sup /spl reg// microprocessors.
This paper proposes an efficient architecture for the two-dimensional inverse discrete wavelet transform (2D IDWT). The proposed architecture includes an inverse transform module, a RAM module, and a multiplexer. In t...
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ISBN:
(纸本)0780374487
This paper proposes an efficient architecture for the two-dimensional inverse discrete wavelet transform (2D IDWT). The proposed architecture includes an inverse transform module, a RAM module, and a multiplexer. In the inverse transform module, we employ the coefficient folding technique and the polyphase decomposition technique to the interpolation filters of stages 1 and 2, respectively. The RAM size is N/2/spl times/N/2. The advantages of the proposed architecture are the 100% hardware utilization, fast computing time, regular dataflow, and low control complexity, making this architecture suitable for next generation image coding/decoding systems.
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