Active networks allow their users to inject customized programs into the nodes of the network. An extreme case, in which we are most interested, replaces packets with "capsules" - program fragments that are ...
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Active networks allow their users to inject customized programs into the nodes of the network. An extreme case, in which we are most interested, replaces packets with "capsules" - program fragments that are executed at each network router/switch they traverse. Active architectures permit a massive increase in the sophistication of the computation that is performed within the network. They enable new applications, especially those based on application-specific multicast, information fusion, and other services that leverage network-based computation and storage. Furthermore, they will accelerate the pace of innovation by decoupling network services from the underlying hardware and allowing new services to be loaded into the infrastructure on demand. In this paper, we describe our vision of an active network architecture, outline our approach to its design, and survey the technologies that can be brought to bear on its implementation. We propose that the research community mount a joint effort to develop and deploy a wide area ActiveNet.
Gateways between IP-based networks and fieldbus systems often create the impression of providing a unique, standardised remote access to automation systems. At second sight, however, it becomes apparent that there are...
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Gateways between IP-based networks and fieldbus systems often create the impression of providing a unique, standardised remote access to automation systems. At second sight, however, it becomes apparent that there are several possibilities on the LAN side with individual strengths and shortcomings. This paper reviews typical functions expected from a fieldbus gateway and investigates the properties of SNMP, LDAP, SQL, HTTP and a specially designed proprietary protocol (IGUANA) with respect to their appropriateness for remote access. Particular emphasis is laid on the restriction these protocols impose on the way the data inside the gateway are structured. We find that none of these approaches fully satisfies all requirements.
A previously described computational model (Ellis et al., 2002, and Goldman and Popel, 2000) for oxygen transport in capillary networks of the hamster cheek pouch retractor muscle is adapted to study the rat extensor ...
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A previously described computational model (Ellis et al., 2002, and Goldman and Popel, 2000) for oxygen transport in capillary networks of the hamster cheek pouch retractor muscle is adapted to study the rat extensor digitorum longus muscle. Biophysical parameters from the literature are combined with experimental measurements to construct a model of capillary network structure and oxygen transport from blood to tissue. We describe how experimental values are related to model parameters, and how numerical simulations can be used to determine the effects of sepsis on oxygen transport heterogeneity and the development of localized tissue hypoxia.
We describe a high-level design method to synthesize multi-phase regular arrays. The method is based on deriving component designs using classical regular (or systolic) array synthesis techniques and composing these s...
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We describe a high-level design method to synthesize multi-phase regular arrays. The method is based on deriving component designs using classical regular (or systolic) array synthesis techniques and composing these separately evolved component designs into a unified global design. Similarity transformations are applied to component designs in the composition stage in order to align dataflow between the phases of the computations. Three transformations are considered: rotation, reflection and translation. The technique is aimed at the design of hardware components for high-throughput embedded systems applications and we demonstrate this by deriving a multi-phase regular array for the 2D DCT algorithm which is widely used in many video communications applications.
Owing to their relative simplicity and wide range of applications, static slices are specifically proposed for software maintenance and program understanding. Unfortunately, in many cases static slices are overly cons...
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Owing to their relative simplicity and wide range of applications, static slices are specifically proposed for software maintenance and program understanding. Unfortunately, in many cases static slices are overly conservative and therefore too large to supply useful information to the software maintainer. Dynamic slicing methods can produce more precise results, but only for one test case. In this paper we introduce the concept of union slices (the union of dynamic slices for many test cases) and suggest using a combination of static and union slices. This way the size of program parts that need to be investigated can be reduced by concentrating on the most important parts first. We performed a series of experiments with our experimental implementation on three medium size C programs. Our initial results suggest that union slices are in most cases far smaller than static slices, and that the growth rate of union slices (by adding more test cases) significantly declines after several representative executions of the program.
Mediaprocessors provide high performance by using both instruction- and data-level parallelism. Because of the increased computing power, transferring data between off- and on-chip memories without slowing down the co...
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Mediaprocessors provide high performance by using both instruction- and data-level parallelism. Because of the increased computing power, transferring data between off- and on-chip memories without slowing down the core processor's performance is challenging. Two methods, data cache and direct memory access, address this problem in different ways.
Together with the development of computer network technology, the automatic collaboration of CIM data activities is becoming an important research issue. Two models are proposed for the research issue: a data activity...
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Together with the development of computer network technology, the automatic collaboration of CIM data activities is becoming an important research issue. Two models are proposed for the research issue: a data activity flow network model called DAF-Net for coordinating interdependent data activities and an agent-based integration model of information systems called AIMIS for integrating distributed and heterogeneous information systems on demand. Additionally, this paper addresses the key design factors of the DAF-Net and also the AIMIS: the structural type of the DAF-Net and the agent interaction protocol of the AIMIS. Statistical methods and PVM (Parallel Virtual Machine) software are employed for the design of the DAF-Net and the AIMIS.
Many common iterative or recursive DSP applications can be represented by synchronous data-flow graphs (SDFGs). A great deal of research has been done attempting to optimize such applications through retiming. However...
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Many common iterative or recursive DSP applications can be represented by synchronous data-flow graphs (SDFGs). A great deal of research has been done attempting to optimize such applications through retiming. However, despite its proven effectiveness in transforming single-rate data-flow graphs to equivalent DFGs with smaller clock periods, the use of retiming for attempting to reduce the execution time of synchronous DFGs has never been explored. In this paper, we do just this. We develop the basic definitions and results necessary to expres and study SDFGs. We review the problems faced when attempting to retime an SDFG in order to minimize clock period and then present algorithms for doing this. Finally, we demonstrate the effectiveness of our methods on several examples.
A number of DSP algorithms involve linear transforms employing weighted sum computations, where the weights are fixed at design time. Add-shift implementation of such a computation results in a dataflow graph that ha...
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ISBN:
(纸本)0769508316
A number of DSP algorithms involve linear transforms employing weighted sum computations, where the weights are fixed at design time. Add-shift implementation of such a computation results in a dataflow graph that has multiple precision variables and functional units. We explore the potential of precision sensitive approach for the high level synthesis of such multi-precision DFGs. We focus on fixed latency implementation of these DFGs. We present register allocation, functional unit binding and scheduling algorithms to exploit the multi-precision nature of such DFGs for area efficient implementation. The proposed approach is fairly generic and could be applied to multi-precision DFGs involving any type of functional units. Significant improvements of upto 27% have been obtained over the conventional high-level synthesis approach.
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