We extend the celebrated result of W. A. Kirk that a metric space X is complete if and only if every Caristi self-mapping for X has a fixed point, to partial metric spaces.
We extend the celebrated result of W. A. Kirk that a metric space X is complete if and only if every Caristi self-mapping for X has a fixed point, to partial metric spaces.
The article presents information on weather watchers, who are architects of domestic dataflows. By following a passionate interest in meteorology, home weather observers define and construct tools. Technology becomes...
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The article presents information on weather watchers, who are architects of domestic dataflows. By following a passionate interest in meteorology, home weather observers define and construct tools. Technology becomes a medium for expressing interests. The home has recently been described as a node on a network, its walls punctured by dataflowing to and from televisions, computers, and telephony. Designing software and building devices provides a methodology for describing climate, and provides a sense of order within the home. Weather observation might also be seen as an attempt to domesticate natural phenomena, to textualize weather and produce data or media for consumption within the home. At the same time, the weather is a symbol of unstable and chaotic forces.
The LHCb experiment is currently being installed at the Large Hadron Collider at CERN (Geneva, Switzerland). In order to reduce the amount of data storage for offline analysis, a trigger system is required. The Level-...
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The LHCb experiment is currently being installed at the Large Hadron Collider at CERN (Geneva, Switzerland). In order to reduce the amount of data storage for offline analysis, a trigger system is required. The Level-0 Decision Unit (LODU) is the central part of the first trigger level. It is a full custom 16 layers board using advanced FPGAs in BGA package. The L0DU receives information from the Level-0 sub-triggers (432 bits @ 80MHz) which transmit the data via high speed optical links running at 1.6Gb/s. The processing is implemented using a 40MHz synchronous pipelined architecture. It performs a simple physical algorithm to compute at 40MHz the Level-0 trigger decision in order to reduce the dataflow down to 1MHz for the next trigger level. The internal design of the processing FPGA is mainly composed by a Partial data Processing (PDP) and a Trigger Definition Unit (TDU). The aim of the PDP is to adjust the clock phase, perform the time alignment, prepare the data for the TDU and monitor the data processing. The TDU is flexible and allows to fully re-configure all the trigger conditions without any re-programming the FPGAs through the Experiment Control System (ECS).
Discusses a computational method for the analysis of complete factorial experiments. Standard order of the data; Standard analysis of variance; Analyses omitting certain levels of one or more factors; Separate analyse...
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Discusses a computational method for the analysis of complete factorial experiments. Standard order of the data; Standard analysis of variance; Analyses omitting certain levels of one or more factors; Separate analyses for some levels of a factor or for combinations of levels of more than one factor; Calculation of mean effect or interaction means.
The new generation of multicore processors and reconfigurable hardware platforms provides a dramatic increase of the available parallelism and processing capabilities. However, one obstacle for exploiting all the prom...
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The new generation of multicore processors and reconfigurable hardware platforms provides a dramatic increase of the available parallelism and processing capabilities. However, one obstacle for exploiting all the promises of such platforms is deeply rooted in sequential thinking. The sequential programming model does not naturally expose potential parallelism that effectively permits to build parallel applications that can be efficiently mapped on different kind of platforms. A shift of paradigmis necessary at all levels of application development to yield portable and scalable implementations on the widest range of heterogeneous platforms. This paper presents a design flow for the hardware and software synthesis of heterogeneous systems allowing to automatically generate hardware and software components as well as appropriate interfaces, from a unique high-level description of the application, based on the dataflow paradigm, running onto heterogeneous architectures composed by reconfigurable hardware units and multicore processors. Experimental results based on the implementation of several video coding algorithms onto heterogeneous platforms are also provided to show the effectiveness of the approach both in terms of portability and scalability.
Program understanding tools are currently not interoperable, leading researchers to waste significant resources reinventing already existing tools. Even commercial environments that have been designed to support the c...
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Program understanding tools are currently not interoperable, leading researchers to waste significant resources reinventing already existing tools. Even commercial environments that have been designed to support the construction of program understanding tools have serious flaws in this regard. This paper discusses CORUM (Common Object-based Re-engineering Unified Model), an architecture to support interoperability between program understanding tools, and it provides several examples of CORUM's use in the construction of new tools for concept recognition and program visualization.
This paper aims to present a methodology to conduct load flow studies of a multi-area power system with constraints on power settings/power limits on the tie lines linking different areas. Two algorithms are proposed ...
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This paper aims to present a methodology to conduct load flow studies of a multi-area power system with constraints on power settings/power limits on the tie lines linking different areas. Two algorithms are proposed and implemented on test systems including a typical regional grid of an Indian power system. The results of the studies are reported and analyzed.
Congestion caused by a large number of interacting TCP flows at a bottleneck network link is different from that caused by a lesser number of flows sending large amounts of data-the former would require cutting do...
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Congestion caused by a large number of interacting TCP flows at a bottleneck network link is different from that caused by a lesser number of flows sending large amounts of data-the former would require cutting down the number of competing flows, while cutting down the data sending rate is sufficient for the latter. However, since existing congestion control schemes view congestion only from a packet- level perspective, they treat both to be the same, resulting in suboptimal performance. We propose two best effort, search-based, session (or flow) level congestion control strategies for the Internet, to complement existing packet-level congestion control schemes. Our strategies control the number of competing flows to optimize for the flow completion rate and the flow completion time. Furthermore, our session control mechanisms do not require any per-flow state or computation at the routers, make no assumption about input traffic characteristics and requirements, avoid starvation of new flows when existing flows do not leave the system, and do not require any end host TCP modifications. Using evaluations under a wide variety of static and varying traffic load conditions, we demonstrate the significant performance and fairness gains that our session control mechanisms provide.
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