Financial systems are nowadays dependent on electronic data processing technology. One of the most frequent causes of failure in this highly sensitive system are overvoltages mostly caused by lightning. This paper des...
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Financial systems are nowadays dependent on electronic data processing technology. One of the most frequent causes of failure in this highly sensitive system are overvoltages mostly caused by lightning. This paper describes how lightning electromagnetic pulse intrudes into computer information systems and causes system damage. Damage prevention is also discussed.
A new thermodynamic function, fugergy, g, has been defined to facilitate computation of the flow availability function, B. The definition of fugergy is dBT=RTo dln g where R is the gas constant and To is the external ...
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A new thermodynamic function, fugergy, g, has been defined to facilitate computation of the flow availability function, B. The definition of fugergy is dBT=RTo dln g where R is the gas constant and To is the external temperature. A formula for the computation of fugergy is also presented; tabulated values of the fugergy are obtained and presented as a function of: the reduced pressure, the reduced temperature and the reduced external temperature. Formulas for fugergy for the special case of a gas obeying the virial equation as well as Van der Waal's equation are presented in the paper. Finally, the method to compute the changes in the flow availability using the fugergy tables is shown. This is illustrated by means of a numerical example.
In wavelet-based video compression, some kernel functions such as block matching, discrete wavelet transform, are essential but with large complexity in computation. If we dissect two functions into the basic matrix-v...
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ISBN:
(纸本)0780365429
In wavelet-based video compression, some kernel functions such as block matching, discrete wavelet transform, are essential but with large complexity in computation. If we dissect two functions into the basic matrix-vector product forms, a unified design for them becomes feasible. In this paper, with carefully extraction the common computation component, a unified one-dimensional systolic array that can perform block matching and wavelet transform is presented. In this design, the input data is serial-in to save the amount of required pins, the dataflow are carefully arranged to simplify the interconnection between computation components. Unlike the other full-search block matching hardware, it does not require either data broadcasting or the parallel adder. When executing a wavelet transform, the dataflow is scheduled simply and effectively. It does not require any interconnecting network or off-chip memory to store intermediate results.
Nowadays, most of the research developed by industry and academia has led to several object-oriented methods that are highly adequate for the development of systems, but most of these methods do not include mechanisms...
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Nowadays, most of the research developed by industry and academia has led to several object-oriented methods that are highly adequate for the development of systems, but most of these methods do not include mechanisms (models) for identifying and specifying user needs and requirements, as well as testing and validating requirements with end users before, during and after development. These considerations are especially important in interactive systems, where the user interaction is very high and the user interface is a significant part of the system. As a result of this weakness, interactive systems developed using such methods can meet all technical requirements, be very robust, and yet be unusable by the end user. This problem explains a large part of the frequently-observed phenomenon whereby large numbers of change requests to modify the services of an application are made after its deployment. As a solution to this problem, we propose a method for integrating a user interface model into the software life-cycle, taking into account user needs and requirements. Also, this approach to the development process ensures the quality of the delivered applications from the end user's point of view.
A 250-MHz microprocessor intended for home computer entertainment consists of a CPU core with 128-b multimedia extensions, two single-instruction, multiple-data (SIMD) very long instruction word (VLIW) vector processo...
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A 250-MHz microprocessor intended for home computer entertainment consists of a CPU core with 128-b multimedia extensions, two single-instruction, multiple-data (SIMD) very long instruction word (VLIW) vector processors containing ten floating-point multiplier accelerators and four floating-point dividers, an MPEG-2 decoder, a ten-channel direct memory access (DMA) controller, and other peripherals with 128-b internal buses on one die. The core is a two-way superscalar MIPS-compatible microprocessor with 16-kB scratch-pad RAM. Each vector processor is a five-way SIMD-VLIW architecture, which is tightly dedicated for specific applications about three-dimensional geometry calculation and physical simulation. A DMA controller connects between main memory and each professor's local memory to conceal memory access penalty. It contains 10.5 M transistors in 17 x 14.1 mm and dissipates 15 W at 1.8 V.
We report on the first complete system-level demonstration of a superconducting digital communication system. In today's digital computer and communication systems, managing dataflow is a major challenge as the s...
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We report on the first complete system-level demonstration of a superconducting digital communication system. In today's digital computer and communication systems, managing dataflow is a major challenge as the systems have to deal with a huge amount of information. A superconductor device may solve this problem, There have been several attempts to make superconducting switching core circuits, but there have been no complete system-level demonstrations. We have built such a system to demonstrate the efficiency of superconducting devices used in a communication system. Our system is focused on parallel processor communication, and consists of PCs as the processor elements at the three nodes, three interface boxes, and a superconductive chip immersed in a 4.2-K cryostat, The interconnection chip operation is essentially packet switching that was designed with a pipeline ring architecture. The interface box consists of parallel-serial converters, serial-parallel converters, a FIFO output buffer, and a level conversion circuit. The network system operates successfully at approximately 100 MHz, and the clock frequency is restricted by the speed of the interface ICs, not by that of the superconductive chip. We also confirmed the 2-GHz operation of the switching chip, and estimate that the total throughput of the system can be increased to more than 10 Gbps.
A novel technique to obtain a rate- and processor-optimal schedule for a fully-static dataflow graph (DFG) onto a multiprocessor system is presented. In this technique, Floyd-Warshall's shortest path algorithm is...
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A novel technique to obtain a rate- and processor-optimal schedule for a fully-static dataflow graph (DFG) onto a multiprocessor system is presented. In this technique, Floyd-Warshall's shortest path algorithm is used to evaluate the relative firing times of the nodes of the given DFG. Despite its implementation simplicity, the proposed technique has a lower time complexity than all the previously proposed techniques. The technique is tested on various benchmark problems to demonstrate its optimal performance.
The radio frequency spectrum, a scarce resource in mobile communications, has to be efficiently utilized with the objective of increasing the network capacity and minimizing the interference. A variety of channel assi...
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The radio frequency spectrum, a scarce resource in mobile communications, has to be efficiently utilized with the objective of increasing the network capacity and minimizing the interference. A variety of channel assignment strategies have been developed to achieve these objectives. Not only the mobility of the wireless user but also different types of wireless multimedia services create uncertainty in demand and non-optimum use of radio resources. As the cell sizes get smaller, there is a greater need for efficient channel assignment algorithms which are desired to dynamically balance the load of the system by performing reassignments when needed. Static schemes are no longer desirable for small cell systems under heavy and non-uniform multi-rate traffic. We propose a dynamic multi-channel assignment algorithm where the assignment decision is assisted by the mobiles. Our algorithm is based on the concept of network flows, which provide us with the framework to uniformly handle all the events occurring in the system including possible degradation and improvement of the existing assignments. This model enables fast local computations and avoids global reconfiguration which prevent other algorithms being practical.
Pointer aliasing analysis is used to determine if two object names containing dereferences and/or field selectors (e.g., *P,9->t) may refer to the same location during execution. Such information is necessary for a...
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Pointer aliasing analysis is used to determine if two object names containing dereferences and/or field selectors (e.g., *P,9->t) may refer to the same location during execution. Such information is necessary for applications such as data-flow-based testers, program understanding tools, and debuggers, but is expensive to calculate with acceptable precision. Incremental algorithms update dataflow information after a program change rather than recomputing it from scratch, under the assumption that the change impact will be limited. Two versions of a practical incremental pointer aliasing algorithm have been developed, based on Landi-Ryder flow- and context-sensitive alias analysis. Empirical results attest to the time savings over exhaustive analysis (a six-fold speedup on average), and the precision of the approximate solution obtained (on average same solution as exhaustive algorithm for 75% of the tests.).
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