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检索条件"主题词=Data Flow Computing"

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Taking the step from meta-information to communication middleware in computational data streams

Taking the step from meta-information to communication middl...

引用

International Symposium on Parallel and Distributed Processing (IPDPS)

作者： B. Plale P. Widener K. Schwan College of Computing Georgia Institute of Technology GA USA

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VLSI processor for reliable stereo matching based on adaptive window-size selection

VLSI processor for reliable stereo matching based on adaptiv...

引用

IEEE International Conference on Robotics and Automation (ICRA)

作者： M. Hariyama T. Takeuchi M. Kameyama Department of Computer and Mathematical Sciences Graduate School of Information Sciences University of Tohoku Sendai Japan

ISBN: (纸本)0780365763

Stereo vision is a well known method to acquire 3D information. One important problem in stereo vision is to establish reliable correspondence between images. Another problem is that the correspondence search is time-consuming. This paper presents a reliable stereo-matching algorithm and a new parallel VLSI processor architecture for stereo matching. One commonly-used method to establish correspondence between images is the SAD (sum of absolute differences) method. A window size is iteratively enlarged to select as small a window for each pixel as possible that can avoid ambiguity based on uniqueness of a minimum of an SAD graph. This process is called a global search. Next, the estimate of the corresponding pixel obtained by the global search is iteratively refined by shrinking the window size. To avoid ambiguity with a small window size, the correspondence estimate obtained by the global search is efficiently used. The proposed algorithm has regular data flow based on iterations of SAD computation so that it is suitable for parallel processing.

关键词： Very large scale integration Parallel processing Pixel data flow computing Layout Intelligent robots Stereo vision Concurrent computing Process design Intelligent systems

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Algorithm level re-computing-a register transfer level concurrent error detection technique 01

Algorithm level re-computing-a register transfer level concu...

引用

IEEE International Conference on Computer-Aided Design

作者： K. Wu R. Karri Department of Electrical and Computer Engineering Polytechnic University Brooklyn NY USA

ISBN: (纸本)9780780372498

In this paper we propose two algorithm-level time redundancy based Concurrent Error Detection (CED) schemes that exploit diversity in a Register Transfer (RT) level implementation. RT level diversity can be achieved either by changing the operation-to-operator allocation (allocation diversity) or by shifting the operands before re-computation (data diversity). By enabling a fault to affect the normal result and the re-computed result in two different ways, RT level diversity yields good CED capability with low area overhead. We used Synopsys Behavior Compiler (BC) to implement the technique.

关键词： Redundancy Circuit faults Hardware Registers Computer errors Error correction Fault detection Logic Combinational circuits data flow computing

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Motivating hierarchical run-time models in measurement and control systems

Motivating hierarchical run-time models in measurement and c...

引用

American Control Conference (ACC)

作者： Jie Liu S. Jefferson E.A. Lee Department of EECS University of California Berkeley CA USA Agilent Laboratories Agilent Technologies Inc. Palo Alto CA USA

Measurement and control systems are intrinsically distributed and real-time, as they contain sensor and actuator nodes that interact with the physical world directly. Embedded software in the computational nodes is responsible for timely reaction to sensor data, and for producing actuation. This paper reviews run-time computation models for this kind of real-time embedded software, from message semantics, message acquisition, and the dataflow/control flow perspectives. In general, dataflow centric models are natural for describing measurement and control algorithms and easy to use in distributed systems, but they lack mechanisms for controlling the execution order to fulfill timing constrains. Control-flow centric models are good at handling real-time requirements but are hard to distribute and sometimes hard to analyze. Although most practical run-time models to some extent support both dataflow and control flow, they are hardly universal. In complex applications, it is desirable to use different models in different parts of the system or under different modes of operation. Cleanly integrating multiple run-time models is a challenging task. In this paper, we motivate a hierarchical architecture for composing run-time models, based on the Ptolemy II component framework and models of computation. Unlike traditional real-time operating systems that provide only one flat layer of abstraction, the hierarchical architecture enhances flexibility, scalability, and reliability of MC systems by mixing and matching multiple run-time models in a disciplined way.

关键词： Runtime Real time systems Embedded software Embedded computing Computational modeling Computer architecture Control systems Sensor systems Actuators data flow computing

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Synchronous programming of automatic control applications using ORCCAD and ESTEREL

Synchronous programming of automatic control applications us...

引用

IEEE Conference on Decision and Control

作者： D. Simon A. Girault INRIA BIP project ZIRST Saint Ismier France

Automatic control systems are typical examples of hybrid systems where continuous time aspects, related to control laws, must be carefully merged with discrete-time aspects related to control switches and exception handling. These two aspects interact in real-time to ensure the nominal behavior of the system and allow for safe and graceful degradation. In a mixed synchronous/asynchronous approach, ranging from user requirements to run-time code, ORCCAD provides formalized control structures, the coordination of which is specified using the ESTEREL synchronous language. ORCCAD is actually a set of CAD tools, that have been designed and integrated to help the users through programming, formal verification, real-time code generation, and implementation processes.

关键词： Automatic programming Automatic control Control systems Real time systems Robotics and automation Application software data flow computing flow graphs Switches Degradation

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Hierarchical modeling and verification of embedded systems

Hierarchical modeling and verification of embedded systems

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Euromicro Symposium on Digital System Design

作者： L.A. Cortes P. Eles Z. Peng Department of Computer and Information Science Linköping University Linkoping Sweden

In order to represent efficiently large systems, a mechanism for hierarchical composition is needed so that the model may be constructed in a structured manner and composed of simpler units easily comprehensible by the designer at each description level. In this paper we formally define the notion of hierarchy for a Petri net based representation used for modeling embedded systems. We show how small parts of a large system may be transformed by using the concept of hierarchy and the advantages of a transformational approach in the verification of embedded systems. A real-life example illustrates the feasibility of our approach on practical applications.

关键词： Embedded system Timing Petri nets Information science Real time systems Process design data flow computing Embedded computing Computational modeling flow graphs

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Evaluating register file size in ASIP design

Evaluating register file size in ASIP design

引用

International Workshop on Hardware/Software Codesign (CODES)

作者： M.K. Jain L. Wehmeyer S. Steinke P. Marwedel M. Balakrishnan Department of Computer Science & Engineering Indian Institute of Technology Delhi India Department of Computer Science 12 University of Dortmund Germany

ISBN: (纸本)1581133642

Interest in synthesis of Application Specific Instruction Set Processors or ASIPs has increased considerably and a number of methodologies have been proposed for ASIP design. A key step in ASIP synthesis involves deciding architectural features based on application requirements and constraints. In this paper we observe the effect of changing register file size on the performance as well as power and energy consumption. Detailed data is generated and analyzed for a number of application programs. Results indicate that choice of an appropriate number of registers has a significant impact on performance.

关键词： Application specific processors Registers Aerospace electronics Space exploration data flow computing Computer science Costs Automatic control Control system synthesis Permission

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An automatic word length determination method

An automatic word length determination method

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： M.-A. Cantin Y. Savaria D. Prodanos P. Lavoie Electrical and Computer Engineering Dept École Polytechnique de Montréal Montreal QUE Canada Nortel Networks Limited Nepean ONT Canada Dept of National Defence Defense Research Establishment Ottawa ONT Canada

ISBN: (纸本)0780366859

A method to determine the word length required by implementations of Digital Signal Processing (DSP) algorithms is presented. The method uses a C/C++ fixed-point simulation tool to model the impact of finite word length on overall accuracy. It finds a combination of quasi-optimum bit resolutions in arbitrary data flow graphs by computing dissimilarities between fixed-point and floating-point simulation results. The selected algorithm minimizes these dissimilarities and finds a combination of word lengths that meets objectives specified by the user. This method is applicable to a wide range of DSP algorithms. It was tested on 2 benchmarks, the fifth order elliptic filter and the Inverse Discrete Cosine Transform (IDCT), and arrived to known optimum solutions.

关键词： Digital signal processing Signal processing algorithms Computational modeling Hardware data flow computing Power dissipation Constellation diagram Signal resolution flow graphs Testing

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Program slicing: methods and applications

Program slicing: methods and applications

引用

IEEE International Workshop on Source Code Analysis and Manipulation

作者： A. De Lucia Faculty of Engineering University of Sannio Benevento Italy

Program slicing is a viable method to restrict the focus of a task to specific sub-components of a program. Examples of applications include debugging, testing, program comprehension, restructuring, downsizing, and parallelization. The paper discusses different statement deletion based slicing methods, together with algorithms and applications to software engineering.

关键词： Application software Debugging Software engineering Testing Software algorithms Programming profession Computer applications data flow computing Equations

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Generating mixed hardware/software systems from SDL specifications

Generating mixed hardware/software systems from SDL specific...

引用

International Workshop on Hardware/Software Codesign (CODES)

作者： F. Slomka M. Dorfel R. Munzenberger Department of Computer Networks and Communication Systems University of Erlangen Nuremberg Erlangen Germany

ISBN: (纸本)1581133642

A new approach for the translation of SDL specifications to a mixed hardware/software system is presented. Based on the computational model of communicating extended finite state machines (EFSM) the control flow is separated from data flow of the SDL process. Hence for the first time it is possible to generate a mixed hardware/software implementation of an SDL process. This technique also reduces the complexity for high-level and register-transfer synthesis tools for the hardware parts of the system. The advantage of this methodology is shown by a design example of a wireless communication chip.

关键词： Hardware Software systems High level synthesis Communication system control Software performance Computational modeling Automata Application software Computer networks data flow computing

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