A 80-MFLOPS 64-bit microprocessor is described that employs superscalar architecture to execute two instructions, including the combination of 64-bit floating-point add and multiply instructions, in one 25-ns cycle si...
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A 80-MFLOPS 64-bit microprocessor is described that employs superscalar architecture to execute two instructions, including the combination of 64-bit floating-point add and multiply instructions, in one 25-ns cycle simultaneously. The processor, implemented in a 0.8- mu m CMOS technology, contains 1300 K transistors. The processor also employs a RISC (reduced instruction set computer) architecture and Harvard-style bus organization. Division is accomplished every 200 ns. A typical performance is 64 MFLOPS.< >
An efficient extraction of character string positions in a document is proposed by using a morphological operator. In regions of character strings, axial edge pixels and diagonal edge pixels are mingled together, but ...
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An efficient extraction of character string positions in a document is proposed by using a morphological operator. In regions of character strings, axial edge pixels and diagonal edge pixels are mingled together, but in other regions, they are distributed separately. Based on this difference in the directional edge pixel distribution between the character and the non-character regions, string positions are extracted directly from arbitrary blocks without any block analysis, in contrast to previous work which requires block analysis to extract string positions (F.M. Wahl et al., 1982; S. Imade et al., 1993). Experiments are conducted on the document images acquired through the scanner, and the proposed method can directly extract the character string positions from the plain text of character blocks, and even from the document containing tables and flow-charts, without any block analysis.
In this paper the architectural models of pipelined computing units with system-level description, those essentially decrease the design cycle for digital signal processing products, are offered. Practical realization...
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In this paper the architectural models of pipelined computing units with system-level description, those essentially decrease the design cycle for digital signal processing products, are offered. Practical realization of the filter, that confirms developed design flow effectiveness with software products Simulink (Mathlab) and Active HDL, Aldec Inc., is given.
The hardware infrastructure, display system, digital signal processor, array and host-computer control software components developed in a joint project are described. A 64-bit wide implementation of Futurebus+ provide...
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The hardware infrastructure, display system, digital signal processor, array and host-computer control software components developed in a joint project are described. A 64-bit wide implementation of Futurebus+ provides backplane transfer rates of 500 to 700 MByte/s for dataflow between array processors, memory, and display modules all being controlled from a host computer workstation. The two million pixel display module supports viewing rates exceeding 36 images per second for single or multiple image streams. Processing is guided by the operator using ball-type or glove-type interactive devices by viewing animation-rate computed images displayed on the screen. One of the hardware modules includes a thirty-two TMS320C40 processor array capable of a peak computation rate of 1.6 GFLOPS and a sustained rate of about 1 GFLOPS on the scan-line oriented algorithms for which the architecture has been optimized.< >
The design of the KISS-16V2, an ASIC DSP core incorporating an extremely flexible architecture, is described. It is a low-power, 1- mu m CMOS DSP with highly parallel architectural functions, and a sophisticated instr...
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The design of the KISS-16V2, an ASIC DSP core incorporating an extremely flexible architecture, is described. It is a low-power, 1- mu m CMOS DSP with highly parallel architectural functions, and a sophisticated instruction set. This DSP was developed to provide an efficient integration of the multitude of functions required in a GSM (Groupe Speciale Mobile) hand held.< >
computing and networking technologies allow the integration of continuous media dataflows to almost every computer system. We particularly focus on the case of the factory and process control plants where audio, anim...
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computing and networking technologies allow the integration of continuous media dataflows to almost every computer system. We particularly focus on the case of the factory and process control plants where audio, animation and video devices will soon take part in the control and the monitoring of manufacturing processes. We propose a MMS-like multimedia application service element (MASE) for the configuration and the management of multimedia devices and continuous media data streams on manufacturing and process control plants. We also propose a novel architecture for real-time distributed systems using a 155.52 Mbit/s ATM network. The system is based on an intelligent communication board integrating a processor and a field programmable gate array component on which MASE and other flexible high level communication functions are implemented. The embedded ATM switch provides high speed communication links inside the workstation. The main advantages of our architecture include: the reduction of the multimedia load imposed on the host processor, the provision of an efficient real-time data service to applications, and the support of the TCP/IP protocol.
The following topics are discussed: information flow; protocols; logics for anonymity and distributed system security; access control; authorization and security policies; and computational analysis of security protoc...
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The following topics are discussed: information flow; protocols; logics for anonymity and distributed system security; access control; authorization and security policies; and computational analysis of security protocols.
RENO is a modified MIPS R10000 register renamer that uses map-table "short-circuiting" to implement dynamic versions of several well-known static optimizations: move elimination, common subexpression elimina...
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RENO is a modified MIPS R10000 register renamer that uses map-table "short-circuiting" to implement dynamic versions of several well-known static optimizations: move elimination, common subexpression elimination, register allocation, and constant folding. Because it implements these optimizations dynamically, RENO can apply optimizations in certain situations where static compilers cannot. Cycle-level simulation shows that RENO dynamically eliminates (i.e. optimizes away) 22% of the dynamic instructions in both SPECint2000 and MediaBench. RENO/sub CF/ is responsible for 12% and 17% of the eliminations, respectively. Because dataflow dependences are collapsed around eliminated instructions, performance improves by 8% and 13%, respectively. Alternatively, because eliminated instructions do not consume issue queue entries, physical registers, or issue, bypass, register file, and execution bandwidth, RENO can be used to absorb the performance impact of a significantly scaled-down execution core.
Real-time Mentat, a programming environment designed to simplify the task of programming real-time applications in distributed and parallel environments, is described. It is based on the same data-driven computation m...
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Real-time Mentat, a programming environment designed to simplify the task of programming real-time applications in distributed and parallel environments, is described. It is based on the same data-driven computation model and object-oriented programming paradigm as Mentat. It provides an easy-to-use mechanism to exploit parallelism, language constructs for the expression and enforcement of timing constraints, and run-time support for scheduling and exciting real-time programs. The Real-time Mentat programming language is an extended C++. The extensions are added to facilitate automatic detection of dataflow and generation of dataflow graphs, to express the timing constraints of individual granules of computation, and to provide scheduling directives for the runtime system. A high-level view of the Real-time Mentat system architecture and programming language constructs is provided.< >
It has been argued that adequate theories of memory and the structure of knowledge largely eliminates the need for a theory of inference. In this formulation what gets inferred is a function of what gets accessed in m...
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It has been argued that adequate theories of memory and the structure of knowledge largely eliminates the need for a theory of inference. In this formulation what gets inferred is a function of what gets accessed in memory. Thus, the structure and the behaviour of the memory organization needs more attention. The knowledge is viewed in terms of a set of linked concepts in memory. So the key question in this context is, how can a large set of concepts in a memory be organized so that relevant concepts can be searched and linked efficiently? This paper proposes a memory organization and describes a mechanism of finding out the correct association among a set of Input concepts. It implements an active search technique to find out the connectivity among input concepts by bridging sequences of concepts. It aims to resolve the word sense ambiguity problem by selecting the correct sense of a word in a given context, The organization centers upon a model based on a modified theory of spreading activation and proposes a notion of concepts flow, originated from dataflow model of computation to implement an active search technique In a computer. The spreading of activation in a concept flow graph is viewed as propagation of concept tokens from one concept node to another until a connectivity is detected.
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