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检索条件"主题词=Data Flow Computing"

共 877 条记录，以下是411-420 订阅

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The fluid computing middleware: bringing application fluidity to the mobile Internet

The fluid computing middleware: bringing application fluidit...

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Symposium on Applications and the Internet (SAINT)

作者： D. Bourges-Waldegg Y. Duponchel M. Graf M. Moser IBM Zurich Research Laboratory Switzerland

The fluid computing middleware allows application data to flow, as a liquid, between devices. The middleware, based on the model-view-controller design pattern, transforms a collection of devices into a cooperative platform and provides application programmers with appropriate abstractions to use generic data management services, such as data replication and synchronization of arbitrary data structures. Relieved from managing this underlying complexity, programmers can focus on developing new application functionality. In particular, they can program applications that seamlessly transition between devices and connectivity degrees, by relying on the fluid real-time optimistic replication mechanism. By shifting the focus from the network and devices to the data, fluid computing enables new interaction paradigms, where users can access and manipulate their data from any of their devices transparently. Applications, then, become multidevice - a characteristic that can be applied to both single-user and collaboration scenarios.

关键词： Computer applications Middleware Mobile computing Internet Programming profession data flow computing Fluid flow data structures Computer networks Collaboration

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A graph-based algorithm of operation binding for compilers targeting heterogeneous datapath

A graph-based algorithm of operation binding for compilers t...

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IEEE Asia-Pacific Conference on Circuits and Systems

作者： N. Ishiura M. Yamaguchi T. Kambe Department Information Systems Engineering Osaka University Suita Osaka Japan Precision Technology Development Center Sharp Corporation Tenri Nara Japan

This paper presents a graph-based binding algorithm for a retargetable compiler which can deal with "heterogeneous" or "non-orthogonal" datapath architectures. In the compilation of programs for such architectures, binding of operations to functional units becomes a hard task because a certain assignment of an operation to a functional unit may make the execution of succeeding operations impossible. Previously, we proposed a BDD-based algorithm to solve the operation binding problem completely, but it is applicable to a limited size of DFGs because it requires large number of Boolean variables. As a remedy to this problem, we propose in this paper a new algorithm which is based on transformations of a graph representing the solution space. The time complexity remains exponential but the new algorithm is better in that it is applicable to larger instances.

关键词： Boolean functions Computer architecture data structures Information systems data engineering Systems engineering and theory Digital systems Embedded software data flow computing Dynamic programming

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Actor-Oriented Modeling and Simulation of Sliding Window Image Processing Algorithms

Actor-Oriented Modeling and Simulation of Sliding Window Ima...

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Embedded Systems for Real-Time Multimedia (ESTIMedia)

作者： Joachim Keinert Joachim Falk Christian Haubelt Jurgen Teich Fraunhofer IIS Erlangen Germany Department of Computer Science 12 University of Erlangen Nuremberg Germany

Embedded real-time image processing systems have to process huge amounts of data with limited resources and energy. Hence high efficiency is not only required for manual, but also for automatic system generation. Therefore, in order to allow for different optimizations, a system specification must be such that important algorithm properties are accessible to the system design software. In this paper, we present a new method how multidimensional image processing algorithms can be modeled by actor-oriented dataflow semantics. Using the example of a binary morphological reconstruction, we investigate the modeling requirements posed by point, local and global image processing algorithms. We show how they can be taken into account in our approach, so that efficient implementation and analysis in terms of buffer size and throughput is possible. In particular, by the explicit specification of the communication behavior, both static and data dependent algorithms are supported allowing for a complete system specification.

关键词： Image processing Algorithm design and analysis Computational modeling Multidimensional systems Image reconstruction Filters Parallel processing data flow computing Scheduling Computer simulation

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Modeling of various addressing schemes for microprocessors using Petri-Net

Modeling of various addressing schemes for microprocessors u...

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IEEE National Conference on Aerospace and Electronics (NAECON)

作者： A.K. Khare G.S. Hura Reynolds and Reynolds Dayton OH USA Department of Computer Science Wright State University Dayton OH USA

Modeling of various features of the Motorola MC6800 microprocessor using PN (Petri net) theory is considered. It is argued that problems faced in the approach by G.S. Hura and J.W. Atwood (1985) will be overcome in the proposed method which provides a unified approach for the program verification of any general microprocessor system. This approach is illustrated through an example.< >

关键词： Petri nets Microprocessor chips data flow computing Control systems Fires Programming profession Computer science Application software Hardware Protocols

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An incremental flow- and context-sensitive pointer aliasing analysis

An incremental flow- and context-sensitive pointer aliasing ...

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International Conference on Software Engineering (ICSE)

作者： J.-S. Yur B.G. Ryder W.A. Landi Department of Computer Science Rutgers University Piscataway NJ USA Siemens Corporate Research Inc. Princeton NJ USA

Pointer aliasing analysis is used to determine if two object names containing dereferences and/or field selectors (e.g., *P,9->t) may refer to the same location during execution. Such information is necessary for applications such as data-flow-based testers, program understanding tools, and debuggers, but is expensive to calculate with acceptable precision. Incremental algorithms update data flow information after a program change rather than recomputing it from scratch, under the assumption that the change impact will be limited. Two versions of a practical incremental pointer aliasing algorithm have been developed, based on Landi-Ryder flow- and context-sensitive alias analysis. Empirical results attest to the time savings over exhaustive analysis (a six-fold speedup on average), and the precision of the approximate solution obtained (on average same solution as exhaustive algorithm for 75% of the tests.).

关键词： Testing Algorithm design and analysis Costs Computer science Program processors Information analysis Permission Petroleum Educational institutions data flow computing

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Increased FPGA capacity enables scalable, flexible CCMs: an example from image processing

Increased FPGA capacity enables scalable, flexible CCMs: an ...

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Annual IEEE Symposium on Field-Programmable Custom computing Machines (FCCM)

作者： J. Greenbaum M. Baxter Ricoh California Research Center Menlo Park CA USA

The need to partition computation across multiple programmable devices in array architecture CCMs leads to performance bottlenecks in data flow through the computer and wiring delays between adjacent devices. However, significant improvements in FPGA capacities have brought one to a threshold where direct inter-chip connections are not required because an entire algorithm can be implemented on a single device for important problems in areas such as image processing. One can now implement architectures that are similar to today's parallel computers in which interprocessor communication is done through shared memory or dedicated communication hardware. The benefits of this approach are system-wide scalability and flexibility. The authors illustrate this new style of CCM with examples from image processing, in particular a novel FPGA implementation of block motion estimation (as for MPEG encoding). Based on the lessons learned from these specific examples, they generalize and speculate on implications for new CCM architectures.

关键词： Field programmable gate arrays data flow computing Computer architecture Image processing Wiring Delay Partitioning algorithms Concurrent computing Hardware Scalability

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High-speed and memory-efficient architecture for 2-D 1-Level discrete wavelet transform

High-speed and memory-efficient architecture for 2-D 1-Level...

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IEEE International Conference on Electronics, Circuits and Systems (ICECS)

作者： Hui Hou Wei Cao Fan-jiong Zhang Jin-mei Lai Jia-rong Tong State Key Lab of ASIC Fudan University Shanghai 201203 china

Two dimensional discrete wavelet transform (2DDWT) has been adopted as a coding tool of JPEG 2000 image coding and MPEG-4 still texture coding. To make it suitable for real-time image processing applications, it is essential to develop custom VLSI chips for computation of 2D-DWT. A new high efficient architecture is proposed for 2D 1-level DWT, with the feature of original data is scanned by group and no temporal buffer is needed. Comparison results show our proposed architecture can provide a higher speed at less hardware consume.

关键词： Discrete wavelet transforms Memory architecture Filters Image coding Hardware Computer architecture MPEG 4 Standard Image processing Very large scale integration data flow computing

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Optimising high-level synthesis for self-checking arithmetic circuits

Optimising high-level synthesis for self-checking arithmetic...

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IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

作者： A. Antola V. Piuri M. Sami Dipartimento di Elettronica e Informazione Politecnico di Milano Milano Italy

Introduction of self-checking capacity in arithmetic systems since the initial steps of high-level synthesis is taken into account, as an alternative to conventional solutions that adopt ad-hoc coding or comparable techniques after the register-level architecture has been fully defined. A technique based on initial partitioning of the data flow Graph into detectable subgraphs is proposed, by which all single errors appearing within one subgraph are detected; an algorithm leading to optimize resource sharing (allocation and binding of both functional units and registers) while keeping minimum latency and optimum number of checkers is discussed.

关键词： High level synthesis Arithmetic flow graphs Delay Resource management Scheduling algorithm data flow computing Throughput Circuit synthesis Electronic mail

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Reconfiguration of electric distribution networks for energy losses reduction

Reconfiguration of electric distribution networks for energy...

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International Conference on Electric Utility Deregulation and Restructuring and Power Technologies (DRPT)

作者： Lin Yang Zhizhong Guo Department of Electrical Engineering Harbin Institute of Technology Harbin Heilongjiang China

An efficient radial distribution network reconfiguration method for minimization of energy losses over intervals of time is presented in this paper. In order to develop a simple and general method to solve the problem of network dynamic reconfiguration, the concept of system state characterization and its relevant applications are introduced in this paper, in which the computational effort required by traditional optimization method is decreased greatly through some appropriate linearization and stepwise correction techniques. The proposed method is based on loop-analysis theory and superimpose theorem, in which the objective is to minimize energy loss while keeping the feeder voltage profile within pre-specified limits. A case study of IEEE-33 bus system demonstrates the rationality and validity of strategies proposed in this paper, and the results illustrate that the proposed approach has a substantial reduction in computational expense while maintaining a high level of accuracy.

关键词： Energy loss Switches Voltage Load flow Computer networks Energy measurement Loss measurement Optimization methods data flow computing Electric variables measurement

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An efficient architecture for two-dimensional discrete wavelet transform

An efficient architecture for two-dimensional discrete wavel...

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International Symposium on VLSI Technology, Systems and Applications

作者： Po-Cheng Wu Liang-Gee Chen DSP/IC Design Laboratory Department of Electrical Engineering Taipei Taiwan

ISBN: (纸本)0780356209

This paper proposes an efficient architecture for the two-dimensional discrete wavelet transform (2-D DWT). The proposed architecture includes a transform module, a RAM module, and a multiplexer. In the transform-module, we employ the polyphase decomposition technique to the decimation filters of stage 1, and the coefficient folding technique to the decimation filters of stage 2. The RAM size is N/2/spl times/N/2. In comparison with other 2-D DWT architectures, the advantages of the proposed architecture are the near 100% hardware utilization, fast computation time, regular data flow, and low complexity control circuit, making this architecture suitable for next generation image compression systems.

关键词： Discrete wavelet transforms Computer architecture Filters Two dimensional displays Discrete transforms Multiplexing Hardware data flow computing Control systems Circuits

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