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检索条件"主题词=Data Flow Computing"

共 877 条记录，以下是411-420 订阅

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Abductive approach to prototyping data flow diagrams

Abductive approach to prototyping data flow diagrams

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Asia-Pacific Conference on Quality Software

作者： E.T.H. Fung City Univ. of Hong Kong China

In this paper, we propose to develop prototypes of data flow diagrams using a logical framework, which is based on an extension of logic programming to perform abductive reasoning (abductive logic programming). Based on the framework, we discuss how to represent a data flow diagram in a declarative manner as a set of logical sentences and outline a proof procedure. Given the declarative representation of a data flow diagram, the proof procedure can be applied, which combines forward and backward chaining in a structured manner. Unlike the conventional logic programming, the computed answers are abducible atoms directly representing the outputs. When restricting to the use of pure Prolog, we provide the semantics of the outputs under the abductive logical framework and show the soundness and completeness of the proof procedure. We compare our approach with conventional backward chaining and finally discuss some further enhancements.

关键词： Prototypes Logic programming Design for disassembly data flow computing

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A data flow fault coverage metric for validation of behavioral HDL descriptions

A data flow fault coverage metric for validation of behavior...

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IEEE International Conference on Computer-Aided Design

作者： Qiushuang Zhang I.G. Harris Department of Electrical and Computer Engineering University of Massachusetts Amherst MA USA

Behavioral HDL descriptions are commonly used to capture the high-level functionality of a hardware circuit for simulation and synthesis. The manual process of creating a behavioral description is error prone, so significant effort must be made to verify the correctness of behavioral descriptions. Simulation-based validation and formal verification are both techniques used to verify correctness. We investigate validation because formal verification techniques are frequently intractable for large designs. The first step toward a behavioral validation technique is the development of a validation fault coverage metric which can be used to evaluate the likelihood of design defect detection with a given test sequence. We propose a validation fault coverage metric which is based on an analysis of the control data flow description associated with the behavior. The proposed metric identifies a subset of paths through the data flow which must be traversed during testing to detect faults. The proposed metric is a tractable compromise between the statement coverage metric which requires only that each statement be executed, and the path coverage metric which requires that all data flow paths be executed. data flow paths are identified based on the relative code locations of definitions and uses of variables which may be assigned incorrectly due to a design error. We propose an efficient method to compute all data flow paths which must be traversed, and we generate coverage results for several benchmark VHDL circuits for comparison to other approaches.

关键词： Hardware design languages Circuit faults Circuit simulation Formal verification Fault detection Testing Circuit synthesis Error correction Fault diagnosis data flow computing

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An efficient extraction of character string positions using morphological operator

An efficient extraction of character string positions using ...

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IEEE International Conference on Systems, Man and Cybernetics

作者： Chang-Joon Park Kyung-Ae Moon Weon-Geun Oh Heung-Moon Choi Kyungpook National University Taegu South Korea Electronics and Telecommunications Research Institute Daejeon South Korea

An efficient extraction of character string positions in a document is proposed by using a morphological operator. In regions of character strings, axial edge pixels and diagonal edge pixels are mingled together, but in other regions, they are distributed separately. Based on this difference in the directional edge pixel distribution between the character and the non-character regions, string positions are extracted directly from arbitrary blocks without any block analysis, in contrast to previous work which requires block analysis to extract string positions (F.M. Wahl et al., 1982; S. Imade et al., 1993). Experiments are conducted on the document images acquired through the scanner, and the proposed method can directly extract the character string positions from the plain text of character blocks, and even from the document containing tables and flow-charts, without any block analysis.

关键词： Pixel data mining flowcharts Character recognition Moon Image analysis Information analysis Image converters data flow computing Labeling

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A generic client/server architecuture for distributed Web-based simulation experimentation

A generic client/server architecuture for distributed Web-ba...

引用

IEEE International Symposium on Computer Aided Control System Design (CACSD)

作者： R. Finsterwalder Wissenschaftliche Einrichtung Math. & Inf. Univ. der Bundeswehr Munchen Neubiberg Germany

ISBN: (纸本)0780365666

The Java language environment, World Wide Web, and client-server architecture are complementary software technologies, which, when used together provide a powerful set of tools for developing and deploying multi-user distributed applications. In this article we describe an approach to build easy-to-use client software as WWW-downloadable Java applets, which use the World Wide Web to interact with servlets running on a remote server. We use this technology for developing a generic framework for remote computation. As application example serves the parametric multicriteria robustness exploration of the dynamics of a high-fidelity aircraft model.

关键词： Computational modeling Java Computer simulation Computer architecture Application software Web sites Concurrent computing Computer interfaces data flow computing Web server

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Stream-oriented FPGA computing in the Streams-C high level language

Stream-oriented FPGA computing in the Streams-C high level l...

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Annual IEEE Symposium on Field-Programmable Custom computing Machines (FCCM)

作者： M. Gokhale J. Stone J. Arnold M. Kalinowski Los Alamos National Laboratory Space Data Systems Group Los Alamos NM USA Princeton NJ USA Adaptive Silicon Inc. Los Gatos CA USA Sarnoff Corporation Princeton NJ USA

ISBN: (纸本)0769508715

Stream oriented processing is an important methodology used in FPGA-based parallel processing. Characteristics of stream-oriented computing include high-data-rate flow of one or more data sources; fixed size, small stream payload (one byte to one word); compute-intensive operations, usually low precision fixed point, on the data stream; access to small local memories holding coefficients and other constants; and occasional synchronization between computational phases. We describe language constructs, compiler technology, and hardware/software libraries embodying the Streams-C system which has been developed to support stream-oriented computation on FPGA-based parallel computers. The language is implemented as a small set of library functions callable from a C language program. The Streams-C compiler synthesizes hardware circuits for multiple FPGAs as well as a multi-threaded software program for the control processor. Our system includes a functional simulation environment based on POSIX threads, allowing the programmer to simulate the collection of parallel processes and their communication at the functional level. Finally we present an application written both in Streams-C and hand-coded in VHDL. Compared to the hand-crafted design, the Streams-C-generated circuit takes 3x the area and runs at 1/2 the clock rate. In terms of time to market, the hand-done design took a month to develop by an experienced hardware developer. The Streams-C design rook a couple of days, for a productivity increase of 10x.

关键词： Field programmable gate arrays High level languages data flow computing Hardware Software libraries Concurrent computing Circuit simulation Parallel processing Payloads Synchronization

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Symbolic debugging scheme for optimized hardware and software

Symbolic debugging scheme for optimized hardware and softwar...

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IEEE International Conference on Computer-Aided Design

作者： F. Koushanfar D. Kirovski M. Potkonjak Electrical Engineeing and Computer Science Departments University of California Los Angeles CA USA Microsoft Research Redmond WA USA

Symbolic debuggers are system development tools that can accelerate the validation speed of behavioral specifications by allowing a user to interact with an executing code at the source level. In response to a user query, the debugger retrieves the value of a source variable in a manner consistent with respect to the source statement where execution has halted. However, when a behavioral specification has been optimized using transformations, values of variables may be inaccessible in the run-time state. We have developed a set of techniques that, given a behavioral specification CDFG, enforce computation of a selected subset V/sub cut/ of user variables such that (i) all other variables /spl upsi//spl isin/CDFG can be computed from V/sub cut/ and (ii) this enforcement has minimal impact on the optimization potential of the computation. The implementation of the new debugging approach poses several optimization tasks. We have formulated the optimization tasks and developed heuristics to solve them. The effectiveness of the approach has been demonstrated on a set of benchmark designs.

关键词： Hardware Software debugging Design optimization Design for disassembly data flow computing Computer science Runtime Displays flow graphs Software tools

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Adoption of structure clash detection method for architectural CAD system generation

Adoption of structure clash detection method for architectur...

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International Symposium on Multimedia Software Engineering

作者： L. Efendy M. Hashimoto T. Hirota Faculty of Computer Science and Systems Engineering Kyushu Institute of Technology Kawazu Japan

As indicated by M.A. Jackson (1975), in order to create a generator to generate an efficient program structure which uses data flow for its constraint computations, we should detect and solve the problem of the clash of input-output data structures. The paper proposes a general framework to characterize the problem of structure clash in the creation of a generator for architectural CAD systems. This framework employs a method using relational inference to detect ordering clash, and at the same time determine the execution sequence of the generated procedural program. Moreover, the paper describes an implementation of this method for generating an object oriented program of a CAD system in the domain of architecture.

关键词： data flow computing Prototypes Character generation Object oriented modeling Design automation Plugs Sockets Computer science data engineering Systems engineering and theory

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A VLSI implementation structure for wavelet decomposition filter

A VLSI implementation structure for wavelet decomposition fi...

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IEEE International Conference on Multimedia and Expo (ICME)

作者： Wu Shunjun Wang Chao Shang Yong Xidian University Xi'an Shaanxi China

In recent years, the wavelet transform has found its wide use in various fields with the fast tower decomposition algorithm as a powerful tool. The DWT just takes the same position in the wavelet analysis as the FFT in the Fourier analysis and so its fast hardware implementation is very crucial to the wavelet application. In this paper, a high-speed implementation structure is derived by introducing the parallel systolic structure into the design of the wavelet decomposition filter. The structure has the advantages of higher computing speed and higher data flowing rate and lower power consumption with the presence of systolic and parallel techniques.

关键词： Very large scale integration Filters Wavelet analysis Wavelet transforms Poles and towers Discrete wavelet transforms Hardware Concurrent computing data flow computing Energy consumption

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Near optimal flow labeling in ATM/IP-LSR networks using multi-segment flows

Near optimal flow labeling in ATM/IP-LSR networks using mult...

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IEEE International Conference on Networks

作者： A. Harwood H. Shen School of Computing and Information Technology Griffith University QLD Australia

Packet or datagram based routing is widely used for the Internet mainly due to its robustness, ease of implementation and autonomous behavior. Hierarchical networks are necessary to provide scalability. Previous developments proposed for ATM technology to be the basis of packet switched routing protocols. This technology provides flows to reduce the number of times a packet's destination address must be looked up in a routing table thereby increasing the performance of the overall system. Basic methods to establish and maintain these flows have emerged. Clearly one cannot define a flow between every (source, destination) pair since the number of destinations (in the Internet) is prohibitively large. We provide a definition of the problem with optimality criteria, and an algorithm that autonomously establishes a dynamic hierarchy of flows over an arbitrary network according to traffic demand. If the network is of size n, our algorithm uses only O(n/sub 0/log/sub n0/n) labels at each router where n/sub 0/=e/spl ap/3. Packets are routed over a /spl lambda/-segmented flow such that the label table is accessed at most /spl lambda/=log/sub n0/n-1 times. We show that the total table look-up complexity, O(n0log/sub n0//sup 2/n), is a factor /spl Theta/(log/sub n0/log/sub n0/n) times the optimal, which makes substantial improvement of other results known to us. Our hierarchy of flows naturally exists transparently on top of the underlying hierarchical address space (IP) and requires no additional information.

关键词： Labeling Intelligent networks Routing Asynchronous transfer mode Packet switching data flow computing Information technology Australia Robustness Scalability

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Evaluation of P/sup 3/T+: a performance estimator for distributed and parallel applications

Evaluation of P/sup 3/T+: a performance estimator for distri...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： T. Fahringer A. Pozgaj J. Luitz H. Moritsch Institute for Software Technology and Parallel Systems University of Technology Vienna Vienna Austria Institute of Physical and Theoretical Chemistry University of Technology Vienna Vienna Austria

In this paper, we report on experiences with P/sup 3/T+, a performance estimator for distributed and parallel programs which is used to examine at compile time the performance outcome of changes in code, problem and machine sizes, and target architectures. P/sup 3/T+ computes a variety of performance parameters including work distribution, number of transfers, amount of data transferred, transfer times, computation times, and number of cache misses. It is unique in that it models programs, code transformations and parallel and distributed architectures and derives a performance prediction based on all three of these elements. P/sup 3/T+ is the successor tool of P/sup 3/T which computed a similar set of performance parameters, however for parallel programs only. P/sup 3/T+ has been re-designed and re-implemented from scratch and goes beyond P/sup 3/T by extending the class of programs that cart be handled and by employing several novel estimation methods (symbolic analysis, simulation, pre-measured kernel codes, etc.). The core part of this paper reports on the evaluation of P/sup 3/T+ to demonstrate both accuracy and usefulness of this tool for realistic kernel codes taken from real-world applications (pricing of financial derivatives and quantum mechanical calculations of solids).

关键词： Computer architecture Read only memory Kernel Programming profession Concurrent computing data flow computing Cost accounting Pricing Solids Electrical capacitance tomography

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