After several decades of meagre rises in patient outcomes, cardiovascular health care is now on the verge of far-reaching, diagnostic, therapeutic, patient management and outcome improvement changes. The reasons can b...
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After several decades of meagre rises in patient outcomes, cardiovascular health care is now on the verge of far-reaching, diagnostic, therapeutic, patient management and outcome improvement changes. The reasons can be summarized as follows: 1) a direct correlation between adequate oxygen delivery and (a) quality of life in general population, and (b) better outcomes in surgical and critically ill patients, has been established in numerous clinical studies; 2) real-time communication of computer acquired and processed medical data via the Internet or intranets is becoming routine; 3) a clinically accurate, real-time, continuous and noninvasive measurement of global blood flow is now available. This contribution brings in a quantitative and qualitative change in the scope of cardiovascular assessment.
The author proposes the re-documentation of programs with outlines. The interesting feature of outlines is that they allow one to contract, as in a zoom, the amount of information necessary to understand programs, eas...
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The author proposes the re-documentation of programs with outlines. The interesting feature of outlines is that they allow one to contract, as in a zoom, the amount of information necessary to understand programs, easing the localization of given computations or identification of the role of a piece of code. As a first stage toward a framework of program outlines, she has defined a model suited to the representation of computations performed within loops. The main feature of the outlines is that they are both formal and conceptual: they are represented within frames which are semantically equivalent to the outlined loop and help understanding what is computed by revealing how this is computed. In order to re-document loops, she implemented a system, PRISME, able to automatically construct outlines of a subset of Lisp looping functions. PRISME allowed one to validate the implementation of the model. Currently, she uses it intensively to experiment the role of outlines for debugging and reverse specification of programs.
To acquire stare-of-the-art hardware at reduced cost, the U.S. Navy is committed to buying commercial off the shelf (COTS) computer hardware. In this rapidly changing technological world, today's hardware will be ...
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To acquire stare-of-the-art hardware at reduced cost, the U.S. Navy is committed to buying commercial off the shelf (COTS) computer hardware. In this rapidly changing technological world, today's hardware will be obsolete tomorrow. The Navy's complex problems often require more computational power than can be delivered by a single serial processor. The solution lies in distributed processing. However, distributed processors tend to have architecture specific languages, requiring an expensive and time-consuming manual rewrite of application software as new technology and new machines become available. The processing graph method (PGM), developed at the Naval Research Laboratory (NRL) in Washington, DC, is an architecture independent method for specifying application software for distributed architectures. Its model of computation is reconfigurable dynamic dataflow: dynamic because the amount of data consumed and produced by an actor may vary from one firing to another; and reconfigurable, because a graph may be disassembled and reassembled. PGM was implemented on the Navy Standard Signal Processor (AN/UYS-2), and on VAX and Sun workstations. The PGMT project at NRL is developing a tool set that will facilitate the implementation of PGM on a given distributed architecture at relatively low cost. We describe the major features PGM and discuss the PGMT project.
In this paper, we present a low power targeted high-level synthesis framework for the synthesis of Multi-Chip Modules (MCM). This new framework is based on minimizing the switching activity on the functional units as ...
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In this paper, we present a low power targeted high-level synthesis framework for the synthesis of Multi-Chip Modules (MCM). This new framework is based on minimizing the switching activity on the functional units as well as the inter-chip buses. The main focus of the developed method is minimizing the power during partitioning and binding phases of high-level synthesis. A Stochastic Evolution based technique has been used for system partitioning. Experimental results were highly encouraging with power reduction of up to 60% on certain benchmark designs.
The n-dimensional grid is one of the most representative patterns of dataflow in parallel computation. The most frequently used scheduling models for grids is the unit execution-unit communication time (UET-UCT). We ...
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The n-dimensional grid is one of the most representative patterns of dataflow in parallel computation. The most frequently used scheduling models for grids is the unit execution-unit communication time (UET-UCT). We enhance the model of n-dimensional grid by adding extra diagonal edges. First, we calculate the optimal makespan for the generalized UET-UCT grid topology and then we establish the minimum number of processors required, to achieve the optimal makespan. Furthermore, we solve the scheduling problem for generalized n-dimensional grids by proposing an optimal time and space scheduling strategy. We thus prove that UET-UCT scheduling of generalized n-dimensional grids is low complexity tractable.
This paper introduces a powerful novel sequencer for controlling computational machines and for structured DMA (direct memory access) applications. It is mainly focused on applications using 2-dimensional memory organ...
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This paper introduces a powerful novel sequencer for controlling computational machines and for structured DMA (direct memory access) applications. It is mainly focused on applications using 2-dimensional memory organization, where most inherent speed-up is obtained thereof. A classification scheme of computational sequencing patterns and storage schemes is derived. In the context of application specific computing the paper illustrates its usefulness especially for data sequencing-recalling examples hereafter published earlier, as far as needed for completeness. The paper also discusses, how the new sequencer hardware provides substantial speed-up compared to traditional sequencing hardware use.
The study is concerned with the development of real time distributed applications and more precisely with the verification of temporal properties in a distributed context (taking into account the characteristics of th...
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The study is concerned with the development of real time distributed applications and more precisely with the verification of temporal properties in a distributed context (taking into account the characteristics of the real architecture). We show how to use a time Petri net based model of the application in order to prove that a communication system (networks, protocols) and a mapping of tasks meet specified temporal properties.
Armstrong III is a 20 node multi-computer that is currently operational. In addition to a RISC processor, each node contains reconfigurable resources implemented with FPGAs. The in-circuit reprogramability of static R...
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Armstrong III is a 20 node multi-computer that is currently operational. In addition to a RISC processor, each node contains reconfigurable resources implemented with FPGAs. The in-circuit reprogramability of static RAM based FPGAs allows the computational capabilities of a node to be dynamically matched to the computational requirements of an application. Most reconfigurable computers in existence today rely solely on a large number of FPGAs to perform computations. In contrast, the paper demonstrates the utility of a small number of FPGAs coupled to a RISC processor with a simple interconnect. The article describes a substantive example application that performs HMM training for speech recognition with the reconfigurable platform.
In this paper, we present a low power targeted high-level synthesis framework for the synthesis of single chip Application Specific DSP (Digital Signal Processing) architectures. This new framework is based on minimiz...
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In this paper, we present a low power targeted high-level synthesis framework for the synthesis of single chip Application Specific DSP (Digital Signal Processing) architectures. This new framework is based on minimizing the switching activity on the functional units as well as the global buses. The main focus of the developed method is minimizing the power during partitioning and binding phases of high-level synthesis. A Stochastic Evolution based technique has been used for partitioning the given dataflow graph describing the DSP algorithm. Experimental results were highly encouraging with power reduction of up to 60% on certain benchmark designs.
The increasing complexity of modem buildings and the client's desire for swift occupation has meant the expeditious completion of the design phase of a project has become ever more important. An effective and work...
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The increasing complexity of modem buildings and the client's desire for swift occupation has meant the expeditious completion of the design phase of a project has become ever more important. An effective and workable design programme is essential to achieve this. Traditionally, building design work has been planned in a perfunctory manner, often in the belief that this creative and iterative process cannot be analyzed and planned in detail. This situation has been perpetuated by a lack of understanding of design information flow and dependency, and the availability of suitable planning techniques. This paper describes a dataflow model of the building design process that is subsequently analyzed in a design structure matrix. The synthesis of these two techniques produces a powerful but easily understood tool to assist in the planning and management of complex, multi-disciplinary building design problems.
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