Load balancing for high-scheduler is scalable, highly available network services demand, borrowed many mature technology, the development of a high-performance server, cluster system is a key component of, this paper ...
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Load balancing for high-scheduler is scalable, highly available network services demand, borrowed many mature technology, the development of a high-performance server, cluster system is a key component of, this paper analyses the development of a network of four needs, details of the three load balancing technology, and accordingly is a load balancing scheduler design, then details of the resulting load balancing for a scheduling system structure of the groups set, finally, load balancing scheduling for specific applications.
The SARTOR project has as one of its goals the development of an environment for the development of correct real-time systems. Modechart is a specification language for real-time systems developed as part of this proj...
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The SARTOR project has as one of its goals the development of an environment for the development of correct real-time systems. Modechart is a specification language for real-time systems developed as part of this project. Verify4 is an implementation of a verifier for certain classes of properties of systems specified using Modechart. The author describes the program Verify4 and addresses implementation issues surrounding three of the key algorithms used in the program.< >
A Service Location Protocol has been designed within the Internet Engineering Task Force to simplify or eliminate the configuration needs for users of the Internet and World-Wide Web. This is of increasing importance ...
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A Service Location Protocol has been designed within the Internet Engineering Task Force to simplify or eliminate the configuration needs for users of the Internet and World-Wide Web. This is of increasing importance to mobile users, first because they experience frequently changing network service environments, and secondly because the Internet is itself becoming more service oriented. The basic Service Location Protocol is described, with detailed descriptions of the various protocol entities, messages, and ways of selecting appropriate services.
Interest in synthesis of Application Specific Instruction Set Processors or ASIPs has increased considerably and a number of methodologies have been proposed for ASIP design. A key step in ASIP synthesis involves deci...
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ISBN:
(纸本)1581133642
Interest in synthesis of Application Specific Instruction Set Processors or ASIPs has increased considerably and a number of methodologies have been proposed for ASIP design. A key step in ASIP synthesis involves deciding architectural features based on application requirements and constraints. In this paper we observe the effect of changing register file size on the performance as well as power and energy consumption. Detailed data is generated and analyzed for a number of application programs. Results indicate that choice of an appropriate number of registers has a significant impact on performance.
Real-time signal processing applications can be described naturally with dataflow graphs. The systems we consider have a mix of real-time and non-real-time processing, where independent dataflow graphs represent tasks...
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Real-time signal processing applications can be described naturally with dataflow graphs. The systems we consider have a mix of real-time and non-real-time processing, where independent dataflow graphs represent tasks and individual dataflow actors are subtasks. Rate-monotonic scheduling is optimal for fixed-priority, preemptive scheduling of periodic tasks. Priority inheritance protocols extend rate-monotonic scheduling theory to include tasks that contend for exclusive access to shared resources. We show that non-preemptive rate-monotonic scheduling can be viewed as preemptive scheduling where the processor is explicitly considered a shared resource. We propose a dynamic, real-time execution model inspired by multithreaded dataflow architectures.
This paper introduces a cooperative computation model of services called CCM which supports dataflow and channel based service computation. The meta-model of CCM is described with MOF (meta-object facility). CCM come...
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This paper introduces a cooperative computation model of services called CCM which supports dataflow and channel based service computation. The meta-model of CCM is described with MOF (meta-object facility). CCM comes from Kahn process network (KPN) model. KPN is a model of computation based on dataflow and commonly used for describing a set of cooperative processes that communicate with each other by means of dataflow. In this paper, we use KPN to model input and output dataflows and interactions among services. CCM uses service description language CCML to describe a service including service operations, service interfaces, sub-services and service interaction. In this paper, we present four kinds of service interaction rules and corresponding interaction events. Finally an application of CCM in a ship information querying system is presented
We present a novel hardware architecture supporting diamond search and fast full search for block matching motion estimation. It can handle irregular dataflow of these fast algorithms without pipeline bubbles, and re...
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ISBN:
(纸本)0780374487
We present a novel hardware architecture supporting diamond search and fast full search for block matching motion estimation. It can handle irregular dataflow of these fast algorithms without pipeline bubbles, and reduce computation of duplicated search positions. The proposed architecture needs preprocessing with a small amount of computational power while performing fast full search and is suitable for the platform-based video coding system. While the diamond search mode can be applied for real-time requirements, we can choose the fast full search mode, which adapts the processing cycles to picture contents and preserves the same quality of full search block matching (FSBM), for applications of high picture quality or compression ratio. It needs only 9K gates and one additional memory of search range size and is more cost-effective than the conventional systolic array architecture.
This paper examines the implementation of pipelined applications using run-time reconfiguration. Throughput and latency of pipelined applications can be significantly improved when reconfiguration is performed at the ...
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This paper examines the implementation of pipelined applications using run-time reconfiguration. Throughput and latency of pipelined applications can be significantly improved when reconfiguration is performed at the level of individual pipeline stages, as opposed to configuration of the entire FPGA. If reconfiguration and execution can be performed simultaneously, the performance of a pipelined application approaches its theoretical maximum. This paper proposes a new FPGA configuration mechanism, called striping, that supports pipeline stage reconfiguration and simultaneous configuration and execution. Additionally, the use of the pipeline stage as the atomic unit of reconfiguration introduces a design abstraction that enables the development families of upwardly-compatible FPGAs and virtual hardware design.
The use of data duplication in systolic architectures to improve the computational time of problems constrained by a large information flow is studied. Its use is demonstrated by presenting an efficient algorithm for ...
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The use of data duplication in systolic architectures to improve the computational time of problems constrained by a large information flow is studied. Its use is demonstrated by presenting an efficient algorithm for sorting N items on a mesh connected computer of N processors. The algorithm has an O(N/sup 1/3/ log N) running time and requires the use of O(N/sup 2/3/) memory locations per processor.< >
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